Nordic Semiconductor Nordic nrf52805 nrf52 1 nRF52805 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller Copyright (c) 2010 - 2020, Nordic Semiconductor ASA\n \n All rights reserved.\n \n Redistribution and use in source and binary forms, with or without modification,\n are permitted provided that the following conditions are met:\n \n 1. Redistributions of source code must retain the above copyright notice, this\n list of conditions and the following disclaimer.\n \n 2. Redistributions in binary form, except as embedded into a Nordic\n Semiconductor ASA integrated circuit in a product or a software update for\n such product, must reproduce the above copyright notice, this list of\n conditions and the following disclaimer in the documentation and/or other\n materials provided with the distribution.\n \n 3. Neither the name of Nordic Semiconductor ASA nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n \n 4. This software, with or without modification, must only be used with a\n Nordic Semiconductor ASA integrated circuit.\n \n 5. Any software provided in binary form under this license must not be reverse\n engineered, decompiled, modified and/or disassembled.\n \n THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS\n OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES\n OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\n GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\n OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n 8 32 32 0x00000000 0xFFFFFFFF CM4 r0p1 little 1 0 3 0 system_nrf52805 NRF_ 2048 2048 112 FICR Factory information configuration registers 0x10000000 0 0x1000 registers FICR 0x20 CODEPAGESIZE Code memory page size 0x010 read-only 0x00001000 CODEPAGESIZE Code memory page size 0 31 CODESIZE Code memory size 0x014 read-only 0x00000030 CODESIZE Code memory size in number of pages 0 31 0x2 0x4 DEVICEID[%s] Description collection: Device identifier 0x060 read-only 0xFFFFFFFF DEVICEID 64 bit unique device identifier 0 31 0x4 0x4 ER[%s] Description collection: Encryption root, word n 0x080 read-only 0xFFFFFFFF ER Encryption root, word n 0 31 0x4 0x4 IR[%s] Description collection: Identity root, word n 0x090 read-only 0xFFFFFFFF IR Identity root, word n 0 31 DEVICEADDRTYPE Device address type 0x0A0 read-only 0xFFFFFFFF DEVICEADDRTYPE Device address type 0 0 Public Public address 0 Random Random address 1 0x2 0x4 DEVICEADDR[%s] Description collection: Device address n 0x0A4 read-only 0xFFFFFFFF DEVICEADDR 48 bit device address 0 31 INFO Device info FICR_INFO read-only 0x100 PART Part code 0x000 read-only 0x00052805 PART Part code 0 31 N52805 nRF52805 0x52805 N52810 nRF52810 0x52810 N52811 nRF52811 0x52811 N52832 nRF52832 0x52832 Unspecified Unspecified 0xFFFFFFFF VARIANT Part variant, hardware version and production configuration 0x004 read-only 0xFFFFFFFF VARIANT Part variant, hardware version and production configuration, encoded as ASCII 0 31 AAAA AAAA 0x41414141 AAA0 AAA0 0x41414130 AABA AABA 0x41414241 AABB AABB 0x41414242 AAB0 AAB0 0x41414230 AACA AACA 0x41414341 AACB AACB 0x41414342 AAC0 AAC0 0x41414330 Unspecified Unspecified 0xFFFFFFFF PACKAGE Package option 0x008 read-only 0xFFFFFFFF PACKAGE Package option 0 31 CA CAxx - WLCSP 0x2004 Unspecified Unspecified 0xFFFFFFFF RAM RAM variant 0x00C read-only 0x00000018 RAM RAM variant 0 31 K24 24 kByte RAM 0x18 Unspecified Unspecified 0xFFFFFFFF FLASH Flash variant 0x010 read-only 0x000000C0 FLASH Flash variant 0 31 K192 192 kByte flash 0xC0 Unspecified Unspecified 0xFFFFFFFF TEMP Registers storing factory TEMP module linearization coefficients FICR_TEMP read-only 0x404 A0 Slope definition A0 0x000 read-only 0xFFFFFFFF A A (slope definition) register 0 11 A1 Slope definition A1 0x004 read-only 0xFFFFFFFF A A (slope definition) register 0 11 A2 Slope definition A2 0x008 read-only 0xFFFFFFFF A A (slope definition) register 0 11 A3 Slope definition A3 0x00C read-only 0xFFFFFFFF A A (slope definition) register 0 11 A4 Slope definition A4 0x010 read-only 0xFFFFFFFF A A (slope definition) register 0 11 A5 Slope definition A5 0x014 read-only 0xFFFFFFFF A A (slope definition) register 0 11 B0 Y-intercept B0 0x018 read-only 0xFFFFFFFF B B (y-intercept) 0 13 B1 Y-intercept B1 0x01C read-only 0xFFFFFFFF B B (y-intercept) 0 13 B2 Y-intercept B2 0x020 read-only 0xFFFFFFFF B B (y-intercept) 0 13 B3 Y-intercept B3 0x024 read-only 0xFFFFFFFF B B (y-intercept) 0 13 B4 Y-intercept B4 0x028 read-only 0xFFFFFFFF B B (y-intercept) 0 13 B5 Y-intercept B5 0x02C read-only 0xFFFFFFFF B B (y-intercept) 0 13 T0 Segment end T0 0x030 read-only 0xFFFFFFFF T T (segment end) register 0 7 T1 Segment end T1 0x034 read-only 0xFFFFFFFF T T (segment end) register 0 7 T2 Segment end T2 0x038 read-only 0xFFFFFFFF T T (segment end) register 0 7 T3 Segment end T3 0x03C read-only 0xFFFFFFFF T T (segment end) register 0 7 T4 Segment end T4 0x040 read-only 0xFFFFFFFF T T (segment end) register 0 7 UICR User information configuration registers 0x10001000 0 0x1000 registers UICR 0x20 0xD 0x4 NRFFW[%s] Description collection: Reserved for Nordic firmware design 0x014 read-write 0xFFFFFFFF NRFFW Reserved for Nordic firmware design 0 31 0xC 0x4 NRFHW[%s] Description collection: Reserved for Nordic hardware design 0x050 read-write 0xFFFFFFFF NRFHW Reserved for Nordic hardware design 0 31 0x20 0x4 CUSTOMER[%s] Description collection: Reserved for customer 0x080 read-write 0xFFFFFFFF CUSTOMER Reserved for customer 0 31 0x2 0x4 PSELRESET[%s] Description collection: Mapping of the nRESET function (see POWER chapter for details) 0x200 read-write 0xFFFFFFFF PIN GPIO pin number onto which nRESET is exposed 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 APPROTECT Access port protection 0x208 read-write 0xFFFFFFFF PALL Enable or disable access port protection. 0 7 Disabled Disable 0xFF Enabled Enable 0x00 BPROT Block Protect 0x40000000 0 0x1000 registers BPROT 0x20 CONFIG0 Block protect configuration register 0 0x600 read-write REGION0 Enable protection for region 0. Write '0' has no effect. 0 0 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION1 Enable protection for region 1. Write '0' has no effect. 1 1 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION2 Enable protection for region 2. Write '0' has no effect. 2 2 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION3 Enable protection for region 3. Write '0' has no effect. 3 3 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION4 Enable protection for region 4. Write '0' has no effect. 4 4 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION5 Enable protection for region 5. Write '0' has no effect. 5 5 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION6 Enable protection for region 6. Write '0' has no effect. 6 6 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION7 Enable protection for region 7. Write '0' has no effect. 7 7 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION8 Enable protection for region 8. Write '0' has no effect. 8 8 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION9 Enable protection for region 9. Write '0' has no effect. 9 9 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION10 Enable protection for region 10. Write '0' has no effect. 10 10 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION11 Enable protection for region 11. Write '0' has no effect. 11 11 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION12 Enable protection for region 12. Write '0' has no effect. 12 12 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION13 Enable protection for region 13. Write '0' has no effect. 13 13 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION14 Enable protection for region 14. Write '0' has no effect. 14 14 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION15 Enable protection for region 15. Write '0' has no effect. 15 15 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION16 Enable protection for region 16. Write '0' has no effect. 16 16 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION17 Enable protection for region 17. Write '0' has no effect. 17 17 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION18 Enable protection for region 18. Write '0' has no effect. 18 18 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION19 Enable protection for region 19. Write '0' has no effect. 19 19 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION20 Enable protection for region 20. Write '0' has no effect. 20 20 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION21 Enable protection for region 21. Write '0' has no effect. 21 21 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION22 Enable protection for region 22. Write '0' has no effect. 22 22 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION23 Enable protection for region 23. Write '0' has no effect. 23 23 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION24 Enable protection for region 24. Write '0' has no effect. 24 24 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION25 Enable protection for region 25. Write '0' has no effect. 25 25 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION26 Enable protection for region 26. Write '0' has no effect. 26 26 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION27 Enable protection for region 27. Write '0' has no effect. 27 27 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION28 Enable protection for region 28. Write '0' has no effect. 28 28 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION29 Enable protection for region 29. Write '0' has no effect. 29 29 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION30 Enable protection for region 30. Write '0' has no effect. 30 30 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION31 Enable protection for region 31. Write '0' has no effect. 31 31 Disabled Protection disabled 0 Enabled Protection enabled 1 CONFIG1 Block protect configuration register 1 0x604 read-write REGION32 Enable protection for region 32. Write '0' has no effect. 0 0 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION33 Enable protection for region 33. Write '0' has no effect. 1 1 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION34 Enable protection for region 34. Write '0' has no effect. 2 2 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION35 Enable protection for region 35. Write '0' has no effect. 3 3 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION36 Enable protection for region 36. Write '0' has no effect. 4 4 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION37 Enable protection for region 37. Write '0' has no effect. 5 5 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION38 Enable protection for region 38. Write '0' has no effect. 6 6 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION39 Enable protection for region 39. Write '0' has no effect. 7 7 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION40 Enable protection for region 40. Write '0' has no effect. 8 8 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION41 Enable protection for region 41. Write '0' has no effect. 9 9 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION42 Enable protection for region 42. Write '0' has no effect. 10 10 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION43 Enable protection for region 43. Write '0' has no effect. 11 11 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION44 Enable protection for region 44. Write '0' has no effect. 12 12 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION45 Enable protection for region 45. Write '0' has no effect. 13 13 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION46 Enable protection for region 46. Write '0' has no effect. 14 14 Disabled Protection disabled 0 Enabled Protection enabled 1 REGION47 Enable protection for region 47. Write '0' has no effect. 15 15 Disabled Protection disabled 0 Enabled Protection enabled 1 DISABLEINDEBUG Disable protection mechanism in debug mode 0x608 read-write 0x00000001 DISABLEINDEBUG Disable the protection mechanism for NVM regions while in debug mode. This register will only disable the protection mechanism if the device is in debug mode. 0 0 Disabled Disabled in debug 1 Enabled Enabled in debug 0 CLOCK Clock control 0x40000000 BPROT 0 0x1000 registers POWER_CLOCK 0 CLOCK 0x20 TASKS_HFCLKSTART Start HFCLK crystal oscillator 0x000 write-only TASKS_HFCLKSTART Start HFCLK crystal oscillator 0 0 Trigger Trigger task 1 TASKS_HFCLKSTOP Stop HFCLK crystal oscillator 0x004 write-only TASKS_HFCLKSTOP Stop HFCLK crystal oscillator 0 0 Trigger Trigger task 1 TASKS_LFCLKSTART Start LFCLK source 0x008 write-only TASKS_LFCLKSTART Start LFCLK source 0 0 Trigger Trigger task 1 TASKS_LFCLKSTOP Stop LFCLK source 0x00C write-only TASKS_LFCLKSTOP Stop LFCLK source 0 0 Trigger Trigger task 1 TASKS_CAL Start calibration of LFRC oscillator 0x010 write-only TASKS_CAL Start calibration of LFRC oscillator 0 0 Trigger Trigger task 1 TASKS_CTSTART Start calibration timer 0x014 write-only TASKS_CTSTART Start calibration timer 0 0 Trigger Trigger task 1 TASKS_CTSTOP Stop calibration timer 0x018 write-only TASKS_CTSTOP Stop calibration timer 0 0 Trigger Trigger task 1 EVENTS_HFCLKSTARTED HFCLK oscillator started 0x100 read-write EVENTS_HFCLKSTARTED HFCLK oscillator started 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_LFCLKSTARTED LFCLK started 0x104 read-write EVENTS_LFCLKSTARTED LFCLK started 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_DONE Calibration of LFCLK RC oscillator complete event 0x10C read-write EVENTS_DONE Calibration of LFCLK RC oscillator complete event 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_CTTO Calibration timer timeout 0x110 read-write EVENTS_CTTO Calibration timer timeout 0 0 NotGenerated Event not generated 0 Generated Event generated 1 INTENSET Enable interrupt 0x304 read-write HFCLKSTARTED Write '1' to enable interrupt for event HFCLKSTARTED 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 LFCLKSTARTED Write '1' to enable interrupt for event LFCLKSTARTED 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 DONE Write '1' to enable interrupt for event DONE 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CTTO Write '1' to enable interrupt for event CTTO 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write HFCLKSTARTED Write '1' to disable interrupt for event HFCLKSTARTED 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 LFCLKSTARTED Write '1' to disable interrupt for event LFCLKSTARTED 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 DONE Write '1' to disable interrupt for event DONE 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CTTO Write '1' to disable interrupt for event CTTO 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 HFCLKRUN Status indicating that HFCLKSTART task has been triggered 0x408 read-only STATUS HFCLKSTART task triggered or not 0 0 NotTriggered Task not triggered 0 Triggered Task triggered 1 HFCLKSTAT HFCLK status 0x40C read-only SRC Source of HFCLK 0 0 RC 64 MHz internal oscillator (HFINT) 0 Xtal 64 MHz crystal oscillator (HFXO) 1 STATE HFCLK state 16 16 NotRunning HFCLK not running 0 Running HFCLK running 1 LFCLKRUN Status indicating that LFCLKSTART task has been triggered 0x414 read-only STATUS LFCLKSTART task triggered or not 0 0 NotTriggered Task not triggered 0 Triggered Task triggered 1 LFCLKSTAT LFCLK status 0x418 read-only SRC Source of LFCLK 0 1 RC 32.768 kHz RC oscillator 0 Xtal 32.768 kHz crystal oscillator 1 Synth 32.768 kHz synthesized from HFCLK 2 STATE LFCLK state 16 16 NotRunning LFCLK not running 0 Running LFCLK running 1 LFCLKSRCCOPY Copy of LFCLKSRC register, set when LFCLKSTART task was triggered 0x41C read-only SRC Clock source 0 1 RC 32.768 kHz RC oscillator 0 Xtal 32.768 kHz crystal oscillator 1 Synth 32.768 kHz synthesized from HFCLK 2 LFCLKSRC Clock source for the LFCLK 0x518 read-write SRC Clock source 0 1 RC 32.768 kHz RC oscillator 0 Xtal 32.768 kHz crystal oscillator 1 Synth 32.768 kHz synthesized from HFCLK 2 BYPASS Enable or disable bypass of LFCLK crystal oscillator with external clock source 16 16 Disabled Disable (use with Xtal or low-swing external source) 0 Enabled Enable (use with rail-to-rail external source) 1 EXTERNAL Enable or disable external source for LFCLK 17 17 Disabled Disable external source (use with Xtal) 0 Enabled Enable use of external source instead of Xtal (SRC needs to be set to Xtal) 1 CTIV Calibration timer interval 0x538 read-write CTIV Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. 0 6 POWER Power control 0x40000000 BPROT 0 0x1000 registers POWER_CLOCK 0 POWER 0x20 TASKS_CONSTLAT Enable Constant Latency mode 0x078 write-only TASKS_CONSTLAT Enable Constant Latency mode 0 0 Trigger Trigger task 1 TASKS_LOWPWR Enable Low-power mode (variable latency) 0x07C write-only TASKS_LOWPWR Enable Low-power mode (variable latency) 0 0 Trigger Trigger task 1 EVENTS_POFWARN Power failure warning 0x108 read-write EVENTS_POFWARN Power failure warning 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_SLEEPENTER CPU entered WFI/WFE sleep 0x114 read-write EVENTS_SLEEPENTER CPU entered WFI/WFE sleep 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_SLEEPEXIT CPU exited WFI/WFE sleep 0x118 read-write EVENTS_SLEEPEXIT CPU exited WFI/WFE sleep 0 0 NotGenerated Event not generated 0 Generated Event generated 1 INTENSET Enable interrupt 0x304 read-write POFWARN Write '1' to enable interrupt for event POFWARN 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 SLEEPENTER Write '1' to enable interrupt for event SLEEPENTER 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 SLEEPEXIT Write '1' to enable interrupt for event SLEEPEXIT 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write POFWARN Write '1' to disable interrupt for event POFWARN 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 SLEEPENTER Write '1' to disable interrupt for event SLEEPENTER 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 SLEEPEXIT Write '1' to disable interrupt for event SLEEPEXIT 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RESETREAS Reset reason 0x400 read-write RESETPIN Reset from pin-reset detected 0 0 NotDetected Not detected 0 Detected Detected 1 DOG Reset from watchdog detected 1 1 NotDetected Not detected 0 Detected Detected 1 SREQ Reset from soft reset detected 2 2 NotDetected Not detected 0 Detected Detected 1 LOCKUP Reset from CPU lock-up detected 3 3 NotDetected Not detected 0 Detected Detected 1 OFF Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO 16 16 NotDetected Not detected 0 Detected Detected 1 DIF Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode 18 18 NotDetected Not detected 0 Detected Detected 1 SYSTEMOFF System OFF register 0x500 write-only SYSTEMOFF Enable System OFF mode 0 0 Enter Enable System OFF mode 1 POFCON Power failure comparator configuration 0x510 read-write POF Enable or disable power failure comparator 0 0 Disabled Disable 0 Enabled Enable 1 THRESHOLD Power failure comparator threshold setting 1 4 V17 Set threshold to 1.7 V 4 V18 Set threshold to 1.8 V 5 V19 Set threshold to 1.9 V 6 V20 Set threshold to 2.0 V 7 V21 Set threshold to 2.1 V 8 V22 Set threshold to 2.2 V 9 V23 Set threshold to 2.3 V 10 V24 Set threshold to 2.4 V 11 V25 Set threshold to 2.5 V 12 V26 Set threshold to 2.6 V 13 V27 Set threshold to 2.7 V 14 V28 Set threshold to 2.8 V 15 GPREGRET General purpose retention register 0x51C read-write GPREGRET General purpose retention register 0 7 GPREGRET2 General purpose retention register 0x520 read-write GPREGRET General purpose retention register 0 7 DCDCEN DC/DC enable register 0x578 read-write DCDCEN Enable or disable DC/DC converter 0 0 Disabled Disable 0 Enabled Enable 1 8 0x010 RAM[%s] Unspecified POWER_RAM read-write 0x900 POWER Description cluster: RAMn power control register. The RAM size will vary depending on product variant, and the RAMn register will only be present if the corresponding RAM AHB slave is present on the device. 0x000 read-write 0x0000FFFF S0POWER Keep RAM section S0 ON or OFF in System ON mode. 0 0 Off Off 0 On On 1 S1POWER Keep RAM section S1 ON or OFF in System ON mode. 1 1 Off Off 0 On On 1 S0RETENTION Keep retention on RAM section S0 when RAM section is in OFF 16 16 Off Off 0 On On 1 S1RETENTION Keep retention on RAM section S1 when RAM section is in OFF 17 17 Off Off 0 On On 1 POWERSET Description cluster: RAMn power control set register 0x004 write-only 0x0000FFFF S0POWER Keep RAM section S0 of RAMn on or off in System ON mode 0 0 On On 1 S1POWER Keep RAM section S1 of RAMn on or off in System ON mode 1 1 On On 1 S0RETENTION Keep retention on RAM section S0 when RAM section is switched off 16 16 On On 1 S1RETENTION Keep retention on RAM section S1 when RAM section is switched off 17 17 On On 1 POWERCLR Description cluster: RAMn power control clear register 0x008 write-only 0x0000FFFF S0POWER Keep RAM section S0 of RAMn on or off in System ON mode 0 0 Off Off 1 S1POWER Keep RAM section S1 of RAMn on or off in System ON mode 1 1 Off Off 1 S0RETENTION Keep retention on RAM section S0 when RAM section is switched off 16 16 Off Off 1 S1RETENTION Keep retention on RAM section S1 when RAM section is switched off 17 17 Off Off 1 P0 GPIO Port 0x50000000 GPIO 0 0x1000 registers GPIO 0x20 OUT Write GPIO port 0x504 read-write PIN0 Pin 0 0 0 Low Pin driver is low 0 High Pin driver is high 1 PIN1 Pin 1 1 1 Low Pin driver is low 0 High Pin driver is high 1 PIN2 Pin 2 2 2 Low Pin driver is low 0 High Pin driver is high 1 PIN3 Pin 3 3 3 Low Pin driver is low 0 High Pin driver is high 1 PIN4 Pin 4 4 4 Low Pin driver is low 0 High Pin driver is high 1 PIN5 Pin 5 5 5 Low Pin driver is low 0 High Pin driver is high 1 PIN6 Pin 6 6 6 Low Pin driver is low 0 High Pin driver is high 1 PIN7 Pin 7 7 7 Low Pin driver is low 0 High Pin driver is high 1 PIN8 Pin 8 8 8 Low Pin driver is low 0 High Pin driver is high 1 PIN9 Pin 9 9 9 Low Pin driver is low 0 High Pin driver is high 1 PIN10 Pin 10 10 10 Low Pin driver is low 0 High Pin driver is high 1 PIN11 Pin 11 11 11 Low Pin driver is low 0 High Pin driver is high 1 PIN12 Pin 12 12 12 Low Pin driver is low 0 High Pin driver is high 1 PIN13 Pin 13 13 13 Low Pin driver is low 0 High Pin driver is high 1 PIN14 Pin 14 14 14 Low Pin driver is low 0 High Pin driver is high 1 PIN15 Pin 15 15 15 Low Pin driver is low 0 High Pin driver is high 1 PIN16 Pin 16 16 16 Low Pin driver is low 0 High Pin driver is high 1 PIN17 Pin 17 17 17 Low Pin driver is low 0 High Pin driver is high 1 PIN18 Pin 18 18 18 Low Pin driver is low 0 High Pin driver is high 1 PIN19 Pin 19 19 19 Low Pin driver is low 0 High Pin driver is high 1 PIN20 Pin 20 20 20 Low Pin driver is low 0 High Pin driver is high 1 PIN21 Pin 21 21 21 Low Pin driver is low 0 High Pin driver is high 1 PIN22 Pin 22 22 22 Low Pin driver is low 0 High Pin driver is high 1 PIN23 Pin 23 23 23 Low Pin driver is low 0 High Pin driver is high 1 PIN24 Pin 24 24 24 Low Pin driver is low 0 High Pin driver is high 1 PIN25 Pin 25 25 25 Low Pin driver is low 0 High Pin driver is high 1 PIN26 Pin 26 26 26 Low Pin driver is low 0 High Pin driver is high 1 PIN27 Pin 27 27 27 Low Pin driver is low 0 High Pin driver is high 1 PIN28 Pin 28 28 28 Low Pin driver is low 0 High Pin driver is high 1 PIN29 Pin 29 29 29 Low Pin driver is low 0 High Pin driver is high 1 PIN30 Pin 30 30 30 Low Pin driver is low 0 High Pin driver is high 1 PIN31 Pin 31 31 31 Low Pin driver is low 0 High Pin driver is high 1 OUTSET Set individual bits in GPIO port 0x508 read-write oneToSet PIN0 Pin 0 0 0 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: a '1' sets the pin high; a '0' has no effect 1 PIN1 Pin 1 1 1 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: a '1' sets the pin high; a '0' has no effect 1 PIN2 Pin 2 2 2 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: a '1' sets the pin high; a '0' has no effect 1 PIN3 Pin 3 3 3 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: a '1' sets the pin high; a '0' has no effect 1 PIN4 Pin 4 4 4 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: a '1' sets the pin high; a '0' has no effect 1 PIN5 Pin 5 5 5 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: a '1' sets the pin high; a '0' has no effect 1 PIN6 Pin 6 6 6 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: a '1' sets the pin high; a '0' has no effect 1 PIN7 Pin 7 7 7 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: a '1' sets the pin high; a '0' has no effect 1 PIN8 Pin 8 8 8 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: a '1' sets the pin high; a '0' has no effect 1 PIN9 Pin 9 9 9 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: a '1' sets the pin high; a '0' has no effect 1 PIN10 Pin 10 10 10 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: a '1' sets the pin high; a '0' has no effect 1 PIN11 Pin 11 11 11 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: a '1' sets the pin high; a '0' has no effect 1 PIN12 Pin 12 12 12 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: a '1' sets the pin high; a '0' has no effect 1 PIN13 Pin 13 13 13 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: a '1' sets the pin high; a '0' has no effect 1 PIN14 Pin 14 14 14 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: a '1' sets the pin high; a '0' has no effect 1 PIN15 Pin 15 15 15 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: a '1' sets the pin high; a '0' has no effect 1 PIN16 Pin 16 16 16 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: a '1' sets the pin high; a '0' has no effect 1 PIN17 Pin 17 17 17 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: a '1' sets the pin high; a '0' has no effect 1 PIN18 Pin 18 18 18 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: a '1' sets the pin high; a '0' has no effect 1 PIN19 Pin 19 19 19 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: a '1' sets the pin high; a '0' has no effect 1 PIN20 Pin 20 20 20 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: a '1' sets the pin high; a '0' has no effect 1 PIN21 Pin 21 21 21 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: a '1' sets the pin high; a '0' has no effect 1 PIN22 Pin 22 22 22 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: a '1' sets the pin high; a '0' has no effect 1 PIN23 Pin 23 23 23 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: a '1' sets the pin high; a '0' has no effect 1 PIN24 Pin 24 24 24 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: a '1' sets the pin high; a '0' has no effect 1 PIN25 Pin 25 25 25 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: a '1' sets the pin high; a '0' has no effect 1 PIN26 Pin 26 26 26 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: a '1' sets the pin high; a '0' has no effect 1 PIN27 Pin 27 27 27 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: a '1' sets the pin high; a '0' has no effect 1 PIN28 Pin 28 28 28 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: a '1' sets the pin high; a '0' has no effect 1 PIN29 Pin 29 29 29 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: a '1' sets the pin high; a '0' has no effect 1 PIN30 Pin 30 30 30 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: a '1' sets the pin high; a '0' has no effect 1 PIN31 Pin 31 31 31 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: a '1' sets the pin high; a '0' has no effect 1 OUTCLR Clear individual bits in GPIO port 0x50C read-write oneToClear PIN0 Pin 0 0 0 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: a '1' sets the pin low; a '0' has no effect 1 PIN1 Pin 1 1 1 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: a '1' sets the pin low; a '0' has no effect 1 PIN2 Pin 2 2 2 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: a '1' sets the pin low; a '0' has no effect 1 PIN3 Pin 3 3 3 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: a '1' sets the pin low; a '0' has no effect 1 PIN4 Pin 4 4 4 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: a '1' sets the pin low; a '0' has no effect 1 PIN5 Pin 5 5 5 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: a '1' sets the pin low; a '0' has no effect 1 PIN6 Pin 6 6 6 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: a '1' sets the pin low; a '0' has no effect 1 PIN7 Pin 7 7 7 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: a '1' sets the pin low; a '0' has no effect 1 PIN8 Pin 8 8 8 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: a '1' sets the pin low; a '0' has no effect 1 PIN9 Pin 9 9 9 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: a '1' sets the pin low; a '0' has no effect 1 PIN10 Pin 10 10 10 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: a '1' sets the pin low; a '0' has no effect 1 PIN11 Pin 11 11 11 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: a '1' sets the pin low; a '0' has no effect 1 PIN12 Pin 12 12 12 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: a '1' sets the pin low; a '0' has no effect 1 PIN13 Pin 13 13 13 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: a '1' sets the pin low; a '0' has no effect 1 PIN14 Pin 14 14 14 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: a '1' sets the pin low; a '0' has no effect 1 PIN15 Pin 15 15 15 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: a '1' sets the pin low; a '0' has no effect 1 PIN16 Pin 16 16 16 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: a '1' sets the pin low; a '0' has no effect 1 PIN17 Pin 17 17 17 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: a '1' sets the pin low; a '0' has no effect 1 PIN18 Pin 18 18 18 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: a '1' sets the pin low; a '0' has no effect 1 PIN19 Pin 19 19 19 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: a '1' sets the pin low; a '0' has no effect 1 PIN20 Pin 20 20 20 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: a '1' sets the pin low; a '0' has no effect 1 PIN21 Pin 21 21 21 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: a '1' sets the pin low; a '0' has no effect 1 PIN22 Pin 22 22 22 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: a '1' sets the pin low; a '0' has no effect 1 PIN23 Pin 23 23 23 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: a '1' sets the pin low; a '0' has no effect 1 PIN24 Pin 24 24 24 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: a '1' sets the pin low; a '0' has no effect 1 PIN25 Pin 25 25 25 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: a '1' sets the pin low; a '0' has no effect 1 PIN26 Pin 26 26 26 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: a '1' sets the pin low; a '0' has no effect 1 PIN27 Pin 27 27 27 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: a '1' sets the pin low; a '0' has no effect 1 PIN28 Pin 28 28 28 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: a '1' sets the pin low; a '0' has no effect 1 PIN29 Pin 29 29 29 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: a '1' sets the pin low; a '0' has no effect 1 PIN30 Pin 30 30 30 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: a '1' sets the pin low; a '0' has no effect 1 PIN31 Pin 31 31 31 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: a '1' sets the pin low; a '0' has no effect 1 IN Read GPIO port 0x510 read-only PIN0 Pin 0 0 0 Low Pin input is low 0 High Pin input is high 1 PIN1 Pin 1 1 1 Low Pin input is low 0 High Pin input is high 1 PIN2 Pin 2 2 2 Low Pin input is low 0 High Pin input is high 1 PIN3 Pin 3 3 3 Low Pin input is low 0 High Pin input is high 1 PIN4 Pin 4 4 4 Low Pin input is low 0 High Pin input is high 1 PIN5 Pin 5 5 5 Low Pin input is low 0 High Pin input is high 1 PIN6 Pin 6 6 6 Low Pin input is low 0 High Pin input is high 1 PIN7 Pin 7 7 7 Low Pin input is low 0 High Pin input is high 1 PIN8 Pin 8 8 8 Low Pin input is low 0 High Pin input is high 1 PIN9 Pin 9 9 9 Low Pin input is low 0 High Pin input is high 1 PIN10 Pin 10 10 10 Low Pin input is low 0 High Pin input is high 1 PIN11 Pin 11 11 11 Low Pin input is low 0 High Pin input is high 1 PIN12 Pin 12 12 12 Low Pin input is low 0 High Pin input is high 1 PIN13 Pin 13 13 13 Low Pin input is low 0 High Pin input is high 1 PIN14 Pin 14 14 14 Low Pin input is low 0 High Pin input is high 1 PIN15 Pin 15 15 15 Low Pin input is low 0 High Pin input is high 1 PIN16 Pin 16 16 16 Low Pin input is low 0 High Pin input is high 1 PIN17 Pin 17 17 17 Low Pin input is low 0 High Pin input is high 1 PIN18 Pin 18 18 18 Low Pin input is low 0 High Pin input is high 1 PIN19 Pin 19 19 19 Low Pin input is low 0 High Pin input is high 1 PIN20 Pin 20 20 20 Low Pin input is low 0 High Pin input is high 1 PIN21 Pin 21 21 21 Low Pin input is low 0 High Pin input is high 1 PIN22 Pin 22 22 22 Low Pin input is low 0 High Pin input is high 1 PIN23 Pin 23 23 23 Low Pin input is low 0 High Pin input is high 1 PIN24 Pin 24 24 24 Low Pin input is low 0 High Pin input is high 1 PIN25 Pin 25 25 25 Low Pin input is low 0 High Pin input is high 1 PIN26 Pin 26 26 26 Low Pin input is low 0 High Pin input is high 1 PIN27 Pin 27 27 27 Low Pin input is low 0 High Pin input is high 1 PIN28 Pin 28 28 28 Low Pin input is low 0 High Pin input is high 1 PIN29 Pin 29 29 29 Low Pin input is low 0 High Pin input is high 1 PIN30 Pin 30 30 30 Low Pin input is low 0 High Pin input is high 1 PIN31 Pin 31 31 31 Low Pin input is low 0 High Pin input is high 1 DIR Direction of GPIO pins 0x514 read-write PIN0 Pin 0 0 0 Input Pin set as input 0 Output Pin set as output 1 PIN1 Pin 1 1 1 Input Pin set as input 0 Output Pin set as output 1 PIN2 Pin 2 2 2 Input Pin set as input 0 Output Pin set as output 1 PIN3 Pin 3 3 3 Input Pin set as input 0 Output Pin set as output 1 PIN4 Pin 4 4 4 Input Pin set as input 0 Output Pin set as output 1 PIN5 Pin 5 5 5 Input Pin set as input 0 Output Pin set as output 1 PIN6 Pin 6 6 6 Input Pin set as input 0 Output Pin set as output 1 PIN7 Pin 7 7 7 Input Pin set as input 0 Output Pin set as output 1 PIN8 Pin 8 8 8 Input Pin set as input 0 Output Pin set as output 1 PIN9 Pin 9 9 9 Input Pin set as input 0 Output Pin set as output 1 PIN10 Pin 10 10 10 Input Pin set as input 0 Output Pin set as output 1 PIN11 Pin 11 11 11 Input Pin set as input 0 Output Pin set as output 1 PIN12 Pin 12 12 12 Input Pin set as input 0 Output Pin set as output 1 PIN13 Pin 13 13 13 Input Pin set as input 0 Output Pin set as output 1 PIN14 Pin 14 14 14 Input Pin set as input 0 Output Pin set as output 1 PIN15 Pin 15 15 15 Input Pin set as input 0 Output Pin set as output 1 PIN16 Pin 16 16 16 Input Pin set as input 0 Output Pin set as output 1 PIN17 Pin 17 17 17 Input Pin set as input 0 Output Pin set as output 1 PIN18 Pin 18 18 18 Input Pin set as input 0 Output Pin set as output 1 PIN19 Pin 19 19 19 Input Pin set as input 0 Output Pin set as output 1 PIN20 Pin 20 20 20 Input Pin set as input 0 Output Pin set as output 1 PIN21 Pin 21 21 21 Input Pin set as input 0 Output Pin set as output 1 PIN22 Pin 22 22 22 Input Pin set as input 0 Output Pin set as output 1 PIN23 Pin 23 23 23 Input Pin set as input 0 Output Pin set as output 1 PIN24 Pin 24 24 24 Input Pin set as input 0 Output Pin set as output 1 PIN25 Pin 25 25 25 Input Pin set as input 0 Output Pin set as output 1 PIN26 Pin 26 26 26 Input Pin set as input 0 Output Pin set as output 1 PIN27 Pin 27 27 27 Input Pin set as input 0 Output Pin set as output 1 PIN28 Pin 28 28 28 Input Pin set as input 0 Output Pin set as output 1 PIN29 Pin 29 29 29 Input Pin set as input 0 Output Pin set as output 1 PIN30 Pin 30 30 30 Input Pin set as input 0 Output Pin set as output 1 PIN31 Pin 31 31 31 Input Pin set as input 0 Output Pin set as output 1 DIRSET DIR set register 0x518 read-write oneToSet PIN0 Set as output pin 0 0 0 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: a '1' sets pin to output; a '0' has no effect 1 PIN1 Set as output pin 1 1 1 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: a '1' sets pin to output; a '0' has no effect 1 PIN2 Set as output pin 2 2 2 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: a '1' sets pin to output; a '0' has no effect 1 PIN3 Set as output pin 3 3 3 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: a '1' sets pin to output; a '0' has no effect 1 PIN4 Set as output pin 4 4 4 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: a '1' sets pin to output; a '0' has no effect 1 PIN5 Set as output pin 5 5 5 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: a '1' sets pin to output; a '0' has no effect 1 PIN6 Set as output pin 6 6 6 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: a '1' sets pin to output; a '0' has no effect 1 PIN7 Set as output pin 7 7 7 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: a '1' sets pin to output; a '0' has no effect 1 PIN8 Set as output pin 8 8 8 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: a '1' sets pin to output; a '0' has no effect 1 PIN9 Set as output pin 9 9 9 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: a '1' sets pin to output; a '0' has no effect 1 PIN10 Set as output pin 10 10 10 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: a '1' sets pin to output; a '0' has no effect 1 PIN11 Set as output pin 11 11 11 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: a '1' sets pin to output; a '0' has no effect 1 PIN12 Set as output pin 12 12 12 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: a '1' sets pin to output; a '0' has no effect 1 PIN13 Set as output pin 13 13 13 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: a '1' sets pin to output; a '0' has no effect 1 PIN14 Set as output pin 14 14 14 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: a '1' sets pin to output; a '0' has no effect 1 PIN15 Set as output pin 15 15 15 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: a '1' sets pin to output; a '0' has no effect 1 PIN16 Set as output pin 16 16 16 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: a '1' sets pin to output; a '0' has no effect 1 PIN17 Set as output pin 17 17 17 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: a '1' sets pin to output; a '0' has no effect 1 PIN18 Set as output pin 18 18 18 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: a '1' sets pin to output; a '0' has no effect 1 PIN19 Set as output pin 19 19 19 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: a '1' sets pin to output; a '0' has no effect 1 PIN20 Set as output pin 20 20 20 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: a '1' sets pin to output; a '0' has no effect 1 PIN21 Set as output pin 21 21 21 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: a '1' sets pin to output; a '0' has no effect 1 PIN22 Set as output pin 22 22 22 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: a '1' sets pin to output; a '0' has no effect 1 PIN23 Set as output pin 23 23 23 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: a '1' sets pin to output; a '0' has no effect 1 PIN24 Set as output pin 24 24 24 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: a '1' sets pin to output; a '0' has no effect 1 PIN25 Set as output pin 25 25 25 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: a '1' sets pin to output; a '0' has no effect 1 PIN26 Set as output pin 26 26 26 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: a '1' sets pin to output; a '0' has no effect 1 PIN27 Set as output pin 27 27 27 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: a '1' sets pin to output; a '0' has no effect 1 PIN28 Set as output pin 28 28 28 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: a '1' sets pin to output; a '0' has no effect 1 PIN29 Set as output pin 29 29 29 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: a '1' sets pin to output; a '0' has no effect 1 PIN30 Set as output pin 30 30 30 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: a '1' sets pin to output; a '0' has no effect 1 PIN31 Set as output pin 31 31 31 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: a '1' sets pin to output; a '0' has no effect 1 DIRCLR DIR clear register 0x51C read-write oneToClear PIN0 Set as input pin 0 0 0 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: a '1' sets pin to input; a '0' has no effect 1 PIN1 Set as input pin 1 1 1 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: a '1' sets pin to input; a '0' has no effect 1 PIN2 Set as input pin 2 2 2 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: a '1' sets pin to input; a '0' has no effect 1 PIN3 Set as input pin 3 3 3 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: a '1' sets pin to input; a '0' has no effect 1 PIN4 Set as input pin 4 4 4 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: a '1' sets pin to input; a '0' has no effect 1 PIN5 Set as input pin 5 5 5 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: a '1' sets pin to input; a '0' has no effect 1 PIN6 Set as input pin 6 6 6 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: a '1' sets pin to input; a '0' has no effect 1 PIN7 Set as input pin 7 7 7 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: a '1' sets pin to input; a '0' has no effect 1 PIN8 Set as input pin 8 8 8 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: a '1' sets pin to input; a '0' has no effect 1 PIN9 Set as input pin 9 9 9 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: a '1' sets pin to input; a '0' has no effect 1 PIN10 Set as input pin 10 10 10 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: a '1' sets pin to input; a '0' has no effect 1 PIN11 Set as input pin 11 11 11 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: a '1' sets pin to input; a '0' has no effect 1 PIN12 Set as input pin 12 12 12 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: a '1' sets pin to input; a '0' has no effect 1 PIN13 Set as input pin 13 13 13 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: a '1' sets pin to input; a '0' has no effect 1 PIN14 Set as input pin 14 14 14 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: a '1' sets pin to input; a '0' has no effect 1 PIN15 Set as input pin 15 15 15 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: a '1' sets pin to input; a '0' has no effect 1 PIN16 Set as input pin 16 16 16 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: a '1' sets pin to input; a '0' has no effect 1 PIN17 Set as input pin 17 17 17 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: a '1' sets pin to input; a '0' has no effect 1 PIN18 Set as input pin 18 18 18 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: a '1' sets pin to input; a '0' has no effect 1 PIN19 Set as input pin 19 19 19 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: a '1' sets pin to input; a '0' has no effect 1 PIN20 Set as input pin 20 20 20 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: a '1' sets pin to input; a '0' has no effect 1 PIN21 Set as input pin 21 21 21 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: a '1' sets pin to input; a '0' has no effect 1 PIN22 Set as input pin 22 22 22 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: a '1' sets pin to input; a '0' has no effect 1 PIN23 Set as input pin 23 23 23 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: a '1' sets pin to input; a '0' has no effect 1 PIN24 Set as input pin 24 24 24 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: a '1' sets pin to input; a '0' has no effect 1 PIN25 Set as input pin 25 25 25 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: a '1' sets pin to input; a '0' has no effect 1 PIN26 Set as input pin 26 26 26 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: a '1' sets pin to input; a '0' has no effect 1 PIN27 Set as input pin 27 27 27 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: a '1' sets pin to input; a '0' has no effect 1 PIN28 Set as input pin 28 28 28 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: a '1' sets pin to input; a '0' has no effect 1 PIN29 Set as input pin 29 29 29 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: a '1' sets pin to input; a '0' has no effect 1 PIN30 Set as input pin 30 30 30 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: a '1' sets pin to input; a '0' has no effect 1 PIN31 Set as input pin 31 31 31 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: a '1' sets pin to input; a '0' has no effect 1 LATCH Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers 0x520 read-write PIN0 Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. 0 0 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN1 Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. 1 1 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN2 Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. 2 2 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN3 Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. 3 3 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN4 Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. 4 4 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN5 Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. 5 5 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN6 Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. 6 6 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN7 Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. 7 7 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN8 Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. 8 8 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN9 Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. 9 9 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN10 Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. 10 10 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN11 Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. 11 11 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN12 Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. 12 12 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN13 Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. 13 13 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN14 Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. 14 14 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN15 Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. 15 15 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN16 Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. 16 16 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN17 Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. 17 17 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN18 Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. 18 18 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN19 Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. 19 19 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN20 Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. 20 20 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN21 Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. 21 21 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN22 Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. 22 22 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN23 Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. 23 23 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN24 Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. 24 24 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN25 Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. 25 25 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN26 Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. 26 26 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN27 Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. 27 27 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN28 Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. 28 28 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN29 Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. 29 29 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN30 Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. 30 30 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN31 Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. 31 31 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 DETECTMODE Select between default DETECT signal behavior and LDETECT mode 0x524 read-write DETECTMODE Select between default DETECT signal behavior and LDETECT mode 0 0 Default DETECT directly connected to PIN DETECT signals 0 LDETECT Use the latched LDETECT behavior 1 0x20 0x4 PIN_CNF[%s] Description collection: Configuration of GPIO pins 0x700 read-write 0x00000002 DIR Pin direction. Same physical register as DIR register 0 0 Input Configure pin as an input pin 0 Output Configure pin as an output pin 1 INPUT Connect or disconnect input buffer 1 1 Connect Connect input buffer 0 Disconnect Disconnect input buffer 1 PULL Pull configuration 2 3 Disabled No pull 0 Pulldown Pull down on pin 1 Pullup Pull up on pin 3 DRIVE Drive configuration 8 10 S0S1 Standard '0', standard '1' 0 H0S1 High drive '0', standard '1' 1 S0H1 Standard '0', high drive '1' 2 H0H1 High drive '0', high 'drive '1'' 3 D0S1 Disconnect '0' standard '1' (normally used for wired-or connections) 4 D0H1 Disconnect '0', high drive '1' (normally used for wired-or connections) 5 S0D1 Standard '0'. disconnect '1' (normally used for wired-and connections) 6 H0D1 High drive '0', disconnect '1' (normally used for wired-and connections) 7 SENSE Pin sensing mechanism 16 17 Disabled Disabled 0 High Sense for high level 2 Low Sense for low level 3 RADIO 2.4 GHz radio 0x40001000 0 0x1000 registers RADIO 1 RADIO 0x20 TASKS_TXEN Enable RADIO in TX mode 0x000 write-only TASKS_TXEN Enable RADIO in TX mode 0 0 Trigger Trigger task 1 TASKS_RXEN Enable RADIO in RX mode 0x004 write-only TASKS_RXEN Enable RADIO in RX mode 0 0 Trigger Trigger task 1 TASKS_START Start RADIO 0x008 write-only TASKS_START Start RADIO 0 0 Trigger Trigger task 1 TASKS_STOP Stop RADIO 0x00C write-only TASKS_STOP Stop RADIO 0 0 Trigger Trigger task 1 TASKS_DISABLE Disable RADIO 0x010 write-only TASKS_DISABLE Disable RADIO 0 0 Trigger Trigger task 1 TASKS_RSSISTART Start the RSSI and take one single sample of the receive signal strength 0x014 write-only TASKS_RSSISTART Start the RSSI and take one single sample of the receive signal strength 0 0 Trigger Trigger task 1 TASKS_RSSISTOP Stop the RSSI measurement 0x018 write-only TASKS_RSSISTOP Stop the RSSI measurement 0 0 Trigger Trigger task 1 TASKS_BCSTART Start the bit counter 0x01C write-only TASKS_BCSTART Start the bit counter 0 0 Trigger Trigger task 1 TASKS_BCSTOP Stop the bit counter 0x020 write-only TASKS_BCSTOP Stop the bit counter 0 0 Trigger Trigger task 1 EVENTS_READY RADIO has ramped up and is ready to be started 0x100 read-write EVENTS_READY RADIO has ramped up and is ready to be started 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_ADDRESS Address sent or received 0x104 read-write EVENTS_ADDRESS Address sent or received 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_PAYLOAD Packet payload sent or received 0x108 read-write EVENTS_PAYLOAD Packet payload sent or received 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_END Packet sent or received 0x10C read-write EVENTS_END Packet sent or received 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_DISABLED RADIO has been disabled 0x110 read-write EVENTS_DISABLED RADIO has been disabled 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_DEVMATCH A device address match occurred on the last received packet 0x114 read-write EVENTS_DEVMATCH A device address match occurred on the last received packet 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_DEVMISS No device address match occurred on the last received packet 0x118 read-write EVENTS_DEVMISS No device address match occurred on the last received packet 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_RSSIEND Sampling of receive signal strength complete 0x11C read-write EVENTS_RSSIEND Sampling of receive signal strength complete 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_BCMATCH Bit counter reached bit count value 0x128 read-write EVENTS_BCMATCH Bit counter reached bit count value 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_CRCOK Packet received with CRC ok 0x130 read-write EVENTS_CRCOK Packet received with CRC ok 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_CRCERROR Packet received with CRC error 0x134 read-write EVENTS_CRCERROR Packet received with CRC error 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_TXREADY RADIO has ramped up and is ready to be started TX path 0x154 read-write EVENTS_TXREADY RADIO has ramped up and is ready to be started TX path 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_RXREADY RADIO has ramped up and is ready to be started RX path 0x158 read-write EVENTS_RXREADY RADIO has ramped up and is ready to be started RX path 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_PHYEND Generated when last bit is sent on air, or received from air 0x16C read-write EVENTS_PHYEND Generated when last bit is sent on air, or received from air 0 0 NotGenerated Event not generated 0 Generated Event generated 1 SHORTS Shortcuts between local events and tasks 0x200 read-write READY_START Shortcut between event READY and task START 0 0 Disabled Disable shortcut 0 Enabled Enable shortcut 1 END_DISABLE Shortcut between event END and task DISABLE 1 1 Disabled Disable shortcut 0 Enabled Enable shortcut 1 DISABLED_TXEN Shortcut between event DISABLED and task TXEN 2 2 Disabled Disable shortcut 0 Enabled Enable shortcut 1 DISABLED_RXEN Shortcut between event DISABLED and task RXEN 3 3 Disabled Disable shortcut 0 Enabled Enable shortcut 1 ADDRESS_RSSISTART Shortcut between event ADDRESS and task RSSISTART 4 4 Disabled Disable shortcut 0 Enabled Enable shortcut 1 END_START Shortcut between event END and task START 5 5 Disabled Disable shortcut 0 Enabled Enable shortcut 1 ADDRESS_BCSTART Shortcut between event ADDRESS and task BCSTART 6 6 Disabled Disable shortcut 0 Enabled Enable shortcut 1 DISABLED_RSSISTOP Shortcut between event DISABLED and task RSSISTOP 8 8 Disabled Disable shortcut 0 Enabled Enable shortcut 1 TXREADY_START Shortcut between event TXREADY and task START 18 18 Disabled Disable shortcut 0 Enabled Enable shortcut 1 RXREADY_START Shortcut between event RXREADY and task START 19 19 Disabled Disable shortcut 0 Enabled Enable shortcut 1 PHYEND_DISABLE Shortcut between event PHYEND and task DISABLE 20 20 Disabled Disable shortcut 0 Enabled Enable shortcut 1 PHYEND_START Shortcut between event PHYEND and task START 21 21 Disabled Disable shortcut 0 Enabled Enable shortcut 1 INTENSET Enable interrupt 0x304 read-write READY Write '1' to enable interrupt for event READY 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ADDRESS Write '1' to enable interrupt for event ADDRESS 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 PAYLOAD Write '1' to enable interrupt for event PAYLOAD 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 END Write '1' to enable interrupt for event END 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 DISABLED Write '1' to enable interrupt for event DISABLED 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 DEVMATCH Write '1' to enable interrupt for event DEVMATCH 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 DEVMISS Write '1' to enable interrupt for event DEVMISS 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 RSSIEND Write '1' to enable interrupt for event RSSIEND 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 BCMATCH Write '1' to enable interrupt for event BCMATCH 10 10 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CRCOK Write '1' to enable interrupt for event CRCOK 12 12 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CRCERROR Write '1' to enable interrupt for event CRCERROR 13 13 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TXREADY Write '1' to enable interrupt for event TXREADY 21 21 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 RXREADY Write '1' to enable interrupt for event RXREADY 22 22 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 PHYEND Write '1' to enable interrupt for event PHYEND 27 27 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write READY Write '1' to disable interrupt for event READY 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ADDRESS Write '1' to disable interrupt for event ADDRESS 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 PAYLOAD Write '1' to disable interrupt for event PAYLOAD 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 END Write '1' to disable interrupt for event END 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 DISABLED Write '1' to disable interrupt for event DISABLED 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 DEVMATCH Write '1' to disable interrupt for event DEVMATCH 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 DEVMISS Write '1' to disable interrupt for event DEVMISS 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RSSIEND Write '1' to disable interrupt for event RSSIEND 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 BCMATCH Write '1' to disable interrupt for event BCMATCH 10 10 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CRCOK Write '1' to disable interrupt for event CRCOK 12 12 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CRCERROR Write '1' to disable interrupt for event CRCERROR 13 13 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TXREADY Write '1' to disable interrupt for event TXREADY 21 21 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RXREADY Write '1' to disable interrupt for event RXREADY 22 22 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 PHYEND Write '1' to disable interrupt for event PHYEND 27 27 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CRCSTATUS CRC status 0x400 read-only CRCSTATUS CRC status of packet received 0 0 CRCError Packet received with CRC error 0 CRCOk Packet received with CRC ok 1 RXMATCH Received address 0x408 read-only RXMATCH Received address 0 2 RXCRC CRC field of previously received packet 0x40C read-only RXCRC CRC field of previously received packet 0 23 DAI Device address match index 0x410 read-only DAI Device address match index 0 2 PDUSTAT Payload status 0x414 read-only PDUSTAT Status on payload length vs. PCNF1.MAXLEN 0 0 LessThan Payload less than PCNF1.MAXLEN 0 GreaterThan Payload greater than PCNF1.MAXLEN 1 PACKETPTR Packet pointer 0x504 read-write 0x00000000 PACKETPTR Packet pointer 0 31 FREQUENCY Frequency 0x508 read-write 0x00000002 FREQUENCY Radio channel frequency 0 6 MAP Channel map selection 8 8 Default Channel map between 2400 MHZ .. 2500 MHz 0 Low Channel map between 2360 MHZ .. 2460 MHz 1 TXPOWER Output power 0x50C read-write TXPOWER RADIO output power 0 7 Pos4dBm +4 dBm 0x4 Pos3dBm +3 dBm 0x3 0dBm 0 dBm 0x0 Neg4dBm -4 dBm 0xFC Neg8dBm -8 dBm 0xF8 Neg12dBm -12 dBm 0xF4 Neg16dBm -16 dBm 0xF0 Neg20dBm -20 dBm 0xEC Neg30dBm Deprecated enumerator - -40 dBm 0xE2 Neg40dBm -40 dBm 0xD8 MODE Data rate and modulation 0x510 read-write MODE Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation. 0 3 Nrf_1Mbit 1 Mbps Nordic proprietary radio mode 0 Nrf_2Mbit 2 Mbps Nordic proprietary radio mode 1 Ble_1Mbit 1 Mbps BLE 3 Ble_2Mbit 2 Mbps BLE 4 PCNF0 Packet configuration register 0 0x514 read-write LFLEN Length on air of LENGTH field in number of bits 0 3 S0LEN Length on air of S0 field in number of bytes 8 8 S1LEN Length on air of S1 field in number of bits 16 19 S1INCL Include or exclude S1 field in RAM 20 20 Automatic Include S1 field in RAM only if S1LEN > 0 0 Include Always include S1 field in RAM independent of S1LEN 1 PLEN Length of preamble on air. Decision point: TASKS_START task 24 25 8bit 8-bit preamble 0 16bit 16-bit preamble 1 CRCINC Indicates if LENGTH field contains CRC or not 26 26 Exclude LENGTH does not contain CRC 0 Include LENGTH includes CRC 1 PCNF1 Packet configuration register 1 0x518 read-write MAXLEN Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. 0 7 STATLEN Static length in number of bytes 8 15 BALEN Base address length in number of bytes 16 18 ENDIAN On-air endianness of packet, this applies to the S0, LENGTH, S1, and the PAYLOAD fields. 24 24 Little Least significant bit on air first 0 Big Most significant bit on air first 1 WHITEEN Enable or disable packet whitening 25 25 Disabled Disable 0 Enabled Enable 1 BASE0 Base address 0 0x51C read-write BASE0 Base address 0 0 31 BASE1 Base address 1 0x520 read-write BASE1 Base address 1 0 31 PREFIX0 Prefixes bytes for logical addresses 0-3 0x524 read-write AP0 Address prefix 0. 0 7 AP1 Address prefix 1. 8 15 AP2 Address prefix 2. 16 23 AP3 Address prefix 3. 24 31 PREFIX1 Prefixes bytes for logical addresses 4-7 0x528 read-write AP4 Address prefix 4. 0 7 AP5 Address prefix 5. 8 15 AP6 Address prefix 6. 16 23 AP7 Address prefix 7. 24 31 TXADDRESS Transmit address select 0x52C read-write TXADDRESS Transmit address select 0 2 RXADDRESSES Receive address select 0x530 read-write ADDR0 Enable or disable reception on logical address 0. 0 0 Disabled Disable 0 Enabled Enable 1 ADDR1 Enable or disable reception on logical address 1. 1 1 Disabled Disable 0 Enabled Enable 1 ADDR2 Enable or disable reception on logical address 2. 2 2 Disabled Disable 0 Enabled Enable 1 ADDR3 Enable or disable reception on logical address 3. 3 3 Disabled Disable 0 Enabled Enable 1 ADDR4 Enable or disable reception on logical address 4. 4 4 Disabled Disable 0 Enabled Enable 1 ADDR5 Enable or disable reception on logical address 5. 5 5 Disabled Disable 0 Enabled Enable 1 ADDR6 Enable or disable reception on logical address 6. 6 6 Disabled Disable 0 Enabled Enable 1 ADDR7 Enable or disable reception on logical address 7. 7 7 Disabled Disable 0 Enabled Enable 1 CRCCNF CRC configuration 0x534 read-write LEN CRC length in number of bytes 0 1 Disabled CRC length is zero and CRC calculation is disabled 0 One CRC length is one byte and CRC calculation is enabled 1 Two CRC length is two bytes and CRC calculation is enabled 2 Three CRC length is three bytes and CRC calculation is enabled 3 SKIPADDR Include or exclude packet address field out of CRC calculation. 8 9 Include CRC calculation includes address field 0 Skip CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. 1 CRCPOLY CRC polynomial 0x538 read-write 0x00000000 CRCPOLY CRC polynomial 0 23 CRCINIT CRC initial value 0x53C read-write CRCINIT CRC initial value 0 23 TIFS Interframe spacing in us 0x544 read-write TIFS Interframe spacing in us. 0 9 RSSISAMPLE RSSI sample 0x548 read-only RSSISAMPLE RSSI sample. 0 6 STATE Current radio state 0x550 read-only STATE Current radio state 0 3 Disabled RADIO is in the Disabled state 0 RxRu RADIO is in the RXRU state 1 RxIdle RADIO is in the RXIDLE state 2 Rx RADIO is in the RX state 3 RxDisable RADIO is in the RXDISABLED state 4 TxRu RADIO is in the TXRU state 9 TxIdle RADIO is in the TXIDLE state 10 Tx RADIO is in the TX state 11 TxDisable RADIO is in the TXDISABLED state 12 DATAWHITEIV Data whitening initial value 0x554 read-write 0x00000040 DATAWHITEIV Data whitening initial value. Bit 6 is hardwired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. 0 6 BCC Bit counter compare 0x560 read-write BCC Bit counter compare 0 31 0x8 0x4 DAB[%s] Description collection: Device address base segment n 0x600 read-write DAB Device address base segment n 0 31 0x8 0x4 DAP[%s] Description collection: Device address prefix n 0x620 read-write DAP Device address prefix n 0 15 DACNF Device address match configuration 0x640 read-write ENA0 Enable or disable device address matching using device address 0 0 0 Disabled Disabled 0 Enabled Enabled 1 ENA1 Enable or disable device address matching using device address 1 1 1 Disabled Disabled 0 Enabled Enabled 1 ENA2 Enable or disable device address matching using device address 2 2 2 Disabled Disabled 0 Enabled Enabled 1 ENA3 Enable or disable device address matching using device address 3 3 3 Disabled Disabled 0 Enabled Enabled 1 ENA4 Enable or disable device address matching using device address 4 4 4 Disabled Disabled 0 Enabled Enabled 1 ENA5 Enable or disable device address matching using device address 5 5 5 Disabled Disabled 0 Enabled Enabled 1 ENA6 Enable or disable device address matching using device address 6 6 6 Disabled Disabled 0 Enabled Enabled 1 ENA7 Enable or disable device address matching using device address 7 7 7 Disabled Disabled 0 Enabled Enabled 1 TXADD0 TxAdd for device address 0 8 8 TXADD1 TxAdd for device address 1 9 9 TXADD2 TxAdd for device address 2 10 10 TXADD3 TxAdd for device address 3 11 11 TXADD4 TxAdd for device address 4 12 12 TXADD5 TxAdd for device address 5 13 13 TXADD6 TxAdd for device address 6 14 14 TXADD7 TxAdd for device address 7 15 15 MODECNF0 Radio mode configuration register 0 0x650 read-write 0x00000200 RU Radio ramp-up time 0 0 Default Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51 0 Fast Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specifications for more information 1 DTX Default TX value 8 9 B1 Transmit '1' 0 B0 Transmit '0' 1 Center Transmit center frequency 2 POWER Peripheral power control 0xFFC read-write 0x00000001 POWER Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. 0 0 Disabled Peripheral is powered off 0 Enabled Peripheral is powered on 1 UART0 Universal Asynchronous Receiver/Transmitter 0x40002000 UART 0 0x1000 registers UARTE0_UART0 2 UART 0x20 TASKS_STARTRX Start UART receiver 0x000 write-only TASKS_STARTRX Start UART receiver 0 0 Trigger Trigger task 1 TASKS_STOPRX Stop UART receiver 0x004 write-only TASKS_STOPRX Stop UART receiver 0 0 Trigger Trigger task 1 TASKS_STARTTX Start UART transmitter 0x008 write-only TASKS_STARTTX Start UART transmitter 0 0 Trigger Trigger task 1 TASKS_STOPTX Stop UART transmitter 0x00C write-only TASKS_STOPTX Stop UART transmitter 0 0 Trigger Trigger task 1 TASKS_SUSPEND Suspend UART 0x01C write-only TASKS_SUSPEND Suspend UART 0 0 Trigger Trigger task 1 EVENTS_CTS CTS is activated (set low). Clear To Send. 0x100 read-write EVENTS_CTS CTS is activated (set low). Clear To Send. 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_NCTS CTS is deactivated (set high). Not Clear To Send. 0x104 read-write EVENTS_NCTS CTS is deactivated (set high). Not Clear To Send. 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_RXDRDY Data received in RXD 0x108 read-write EVENTS_RXDRDY Data received in RXD 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_TXDRDY Data sent from TXD 0x11C read-write EVENTS_TXDRDY Data sent from TXD 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_ERROR Error detected 0x124 read-write EVENTS_ERROR Error detected 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_RXTO Receiver timeout 0x144 read-write EVENTS_RXTO Receiver timeout 0 0 NotGenerated Event not generated 0 Generated Event generated 1 SHORTS Shortcuts between local events and tasks 0x200 read-write CTS_STARTRX Shortcut between event CTS and task STARTRX 3 3 Disabled Disable shortcut 0 Enabled Enable shortcut 1 NCTS_STOPRX Shortcut between event NCTS and task STOPRX 4 4 Disabled Disable shortcut 0 Enabled Enable shortcut 1 INTENSET Enable interrupt 0x304 read-write CTS Write '1' to enable interrupt for event CTS 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 NCTS Write '1' to enable interrupt for event NCTS 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 RXDRDY Write '1' to enable interrupt for event RXDRDY 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TXDRDY Write '1' to enable interrupt for event TXDRDY 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ERROR Write '1' to enable interrupt for event ERROR 9 9 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 RXTO Write '1' to enable interrupt for event RXTO 17 17 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write CTS Write '1' to disable interrupt for event CTS 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 NCTS Write '1' to disable interrupt for event NCTS 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RXDRDY Write '1' to disable interrupt for event RXDRDY 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TXDRDY Write '1' to disable interrupt for event TXDRDY 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ERROR Write '1' to disable interrupt for event ERROR 9 9 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RXTO Write '1' to disable interrupt for event RXTO 17 17 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ERRORSRC Error source 0x480 read-write oneToClear OVERRUN Overrun error 0 0 read NotPresent Read: error not present 0 Present Read: error present 1 PARITY Parity error 1 1 read NotPresent Read: error not present 0 Present Read: error present 1 FRAMING Framing error occurred 2 2 read NotPresent Read: error not present 0 Present Read: error present 1 BREAK Break condition 3 3 read NotPresent Read: error not present 0 Present Read: error present 1 ENABLE Enable UART 0x500 read-write ENABLE Enable or disable UART 0 3 Disabled Disable UART 0 Enabled Enable UART 4 PSEL Unspecified UART_PSEL read-write 0x508 RTS Pin select for RTS 0x000 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 TXD Pin select for TXD 0x004 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 CTS Pin select for CTS 0x008 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 RXD Pin select for RXD 0x00C read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 RXD RXD register 0x518 read-only modifyExternal RXD RX data received in previous transfers, double buffered 0 7 TXD TXD register 0x51C write-only TXD TX data to be transferred 0 7 BAUDRATE Baud rate. Accuracy depends on the HFCLK source selected. 0x524 read-write 0x04000000 BAUDRATE Baud rate 0 31 Baud1200 1200 baud (actual rate: 1205) 0x0004F000 Baud2400 2400 baud (actual rate: 2396) 0x0009D000 Baud4800 4800 baud (actual rate: 4808) 0x0013B000 Baud9600 9600 baud (actual rate: 9598) 0x00275000 Baud14400 14400 baud (actual rate: 14414) 0x003B0000 Baud19200 19200 baud (actual rate: 19208) 0x004EA000 Baud28800 28800 baud (actual rate: 28829) 0x0075F000 Baud31250 31250 baud 0x00800000 Baud38400 38400 baud (actual rate: 38462) 0x009D5000 Baud56000 56000 baud (actual rate: 55944) 0x00E50000 Baud57600 57600 baud (actual rate: 57762) 0x00EBF000 Baud76800 76800 baud (actual rate: 76923) 0x013A9000 Baud115200 115200 baud (actual rate: 115942) 0x01D7E000 Baud230400 230400 baud (actual rate: 231884) 0x03AFB000 Baud250000 250000 baud 0x04000000 Baud460800 460800 baud (actual rate: 470588) 0x075F7000 Baud921600 921600 baud (actual rate: 941176) 0x0EBED000 Baud1M 1Mega baud 0x10000000 CONFIG Configuration of parity and hardware flow control 0x56C read-write HWFC Hardware flow control 0 0 Disabled Disabled 0 Enabled Enabled 1 PARITY Parity 1 3 Excluded Exclude parity bit 0x0 Included Include parity bit 0x7 STOP Stop bits 4 4 One One stop bit 0 Two Two stop bits 1 UARTE0 UART with EasyDMA 0x40002000 UART0 UARTE 0 0x1000 registers UARTE0_UART0 2 UARTE 0x20 TASKS_STARTRX Start UART receiver 0x000 write-only TASKS_STARTRX Start UART receiver 0 0 Trigger Trigger task 1 TASKS_STOPRX Stop UART receiver 0x004 write-only TASKS_STOPRX Stop UART receiver 0 0 Trigger Trigger task 1 TASKS_STARTTX Start UART transmitter 0x008 write-only TASKS_STARTTX Start UART transmitter 0 0 Trigger Trigger task 1 TASKS_STOPTX Stop UART transmitter 0x00C write-only TASKS_STOPTX Stop UART transmitter 0 0 Trigger Trigger task 1 TASKS_FLUSHRX Flush RX FIFO into RX buffer 0x02C write-only TASKS_FLUSHRX Flush RX FIFO into RX buffer 0 0 Trigger Trigger task 1 EVENTS_CTS CTS is activated (set low). Clear To Send. 0x100 read-write EVENTS_CTS CTS is activated (set low). Clear To Send. 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_NCTS CTS is deactivated (set high). Not Clear To Send. 0x104 read-write EVENTS_NCTS CTS is deactivated (set high). Not Clear To Send. 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_RXDRDY Data received in RXD (but potentially not yet transferred to Data RAM) 0x108 read-write EVENTS_RXDRDY Data received in RXD (but potentially not yet transferred to Data RAM) 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_ENDRX Receive buffer is filled up 0x110 read-write EVENTS_ENDRX Receive buffer is filled up 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_TXDRDY Data sent from TXD 0x11C read-write EVENTS_TXDRDY Data sent from TXD 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_ENDTX Last TX byte transmitted 0x120 read-write EVENTS_ENDTX Last TX byte transmitted 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_ERROR Error detected 0x124 read-write EVENTS_ERROR Error detected 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_RXTO Receiver timeout 0x144 read-write EVENTS_RXTO Receiver timeout 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_RXSTARTED UART receiver has started 0x14C read-write EVENTS_RXSTARTED UART receiver has started 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_TXSTARTED UART transmitter has started 0x150 read-write EVENTS_TXSTARTED UART transmitter has started 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_TXSTOPPED Transmitter stopped 0x158 read-write EVENTS_TXSTOPPED Transmitter stopped 0 0 NotGenerated Event not generated 0 Generated Event generated 1 SHORTS Shortcuts between local events and tasks 0x200 read-write ENDRX_STARTRX Shortcut between event ENDRX and task STARTRX 5 5 Disabled Disable shortcut 0 Enabled Enable shortcut 1 ENDRX_STOPRX Shortcut between event ENDRX and task STOPRX 6 6 Disabled Disable shortcut 0 Enabled Enable shortcut 1 INTEN Enable or disable interrupt 0x300 read-write CTS Enable or disable interrupt for event CTS 0 0 Disabled Disable 0 Enabled Enable 1 NCTS Enable or disable interrupt for event NCTS 1 1 Disabled Disable 0 Enabled Enable 1 RXDRDY Enable or disable interrupt for event RXDRDY 2 2 Disabled Disable 0 Enabled Enable 1 ENDRX Enable or disable interrupt for event ENDRX 4 4 Disabled Disable 0 Enabled Enable 1 TXDRDY Enable or disable interrupt for event TXDRDY 7 7 Disabled Disable 0 Enabled Enable 1 ENDTX Enable or disable interrupt for event ENDTX 8 8 Disabled Disable 0 Enabled Enable 1 ERROR Enable or disable interrupt for event ERROR 9 9 Disabled Disable 0 Enabled Enable 1 RXTO Enable or disable interrupt for event RXTO 17 17 Disabled Disable 0 Enabled Enable 1 RXSTARTED Enable or disable interrupt for event RXSTARTED 19 19 Disabled Disable 0 Enabled Enable 1 TXSTARTED Enable or disable interrupt for event TXSTARTED 20 20 Disabled Disable 0 Enabled Enable 1 TXSTOPPED Enable or disable interrupt for event TXSTOPPED 22 22 Disabled Disable 0 Enabled Enable 1 INTENSET Enable interrupt 0x304 read-write CTS Write '1' to enable interrupt for event CTS 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 NCTS Write '1' to enable interrupt for event NCTS 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 RXDRDY Write '1' to enable interrupt for event RXDRDY 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ENDRX Write '1' to enable interrupt for event ENDRX 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TXDRDY Write '1' to enable interrupt for event TXDRDY 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ENDTX Write '1' to enable interrupt for event ENDTX 8 8 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ERROR Write '1' to enable interrupt for event ERROR 9 9 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 RXTO Write '1' to enable interrupt for event RXTO 17 17 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 RXSTARTED Write '1' to enable interrupt for event RXSTARTED 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TXSTARTED Write '1' to enable interrupt for event TXSTARTED 20 20 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TXSTOPPED Write '1' to enable interrupt for event TXSTOPPED 22 22 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write CTS Write '1' to disable interrupt for event CTS 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 NCTS Write '1' to disable interrupt for event NCTS 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RXDRDY Write '1' to disable interrupt for event RXDRDY 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENDRX Write '1' to disable interrupt for event ENDRX 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TXDRDY Write '1' to disable interrupt for event TXDRDY 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENDTX Write '1' to disable interrupt for event ENDTX 8 8 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ERROR Write '1' to disable interrupt for event ERROR 9 9 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RXTO Write '1' to disable interrupt for event RXTO 17 17 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RXSTARTED Write '1' to disable interrupt for event RXSTARTED 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TXSTARTED Write '1' to disable interrupt for event TXSTARTED 20 20 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TXSTOPPED Write '1' to disable interrupt for event TXSTOPPED 22 22 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ERRORSRC Error source This register is read/write one to clear. 0x480 read-write oneToClear OVERRUN Overrun error 0 0 read NotPresent Read: error not present 0 Present Read: error present 1 PARITY Parity error 1 1 read NotPresent Read: error not present 0 Present Read: error present 1 FRAMING Framing error occurred 2 2 read NotPresent Read: error not present 0 Present Read: error present 1 BREAK Break condition 3 3 read NotPresent Read: error not present 0 Present Read: error present 1 ENABLE Enable UART 0x500 read-write ENABLE Enable or disable UARTE 0 3 Disabled Disable UARTE 0 Enabled Enable UARTE 8 PSEL Unspecified UARTE_PSEL read-write 0x508 RTS Pin select for RTS signal 0x000 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 TXD Pin select for TXD signal 0x004 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 CTS Pin select for CTS signal 0x008 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 RXD Pin select for RXD signal 0x00C read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 BAUDRATE Baud rate. Accuracy depends on the HFCLK source selected. 0x524 read-write 0x04000000 BAUDRATE Baud rate 0 31 Baud1200 1200 baud (actual rate: 1205) 0x0004F000 Baud2400 2400 baud (actual rate: 2396) 0x0009D000 Baud4800 4800 baud (actual rate: 4808) 0x0013B000 Baud9600 9600 baud (actual rate: 9598) 0x00275000 Baud14400 14400 baud (actual rate: 14401) 0x003AF000 Baud19200 19200 baud (actual rate: 19208) 0x004EA000 Baud28800 28800 baud (actual rate: 28777) 0x0075C000 Baud31250 31250 baud 0x00800000 Baud38400 38400 baud (actual rate: 38369) 0x009D0000 Baud56000 56000 baud (actual rate: 55944) 0x00E50000 Baud57600 57600 baud (actual rate: 57554) 0x00EB0000 Baud76800 76800 baud (actual rate: 76923) 0x013A9000 Baud115200 115200 baud (actual rate: 115108) 0x01D60000 Baud230400 230400 baud (actual rate: 231884) 0x03B00000 Baud250000 250000 baud 0x04000000 Baud460800 460800 baud (actual rate: 457143) 0x07400000 Baud921600 921600 baud (actual rate: 941176) 0x0F000000 Baud1M 1 megabaud 0x10000000 RXD RXD EasyDMA channel UARTE_RXD read-write 0x534 PTR Data pointer 0x000 read-write PTR Data pointer 0 31 MAXCNT Maximum number of bytes in receive buffer 0x004 read-write MAXCNT Maximum number of bytes in receive buffer 0 9 AMOUNT Number of bytes transferred in the last transaction 0x008 read-only AMOUNT Number of bytes transferred in the last transaction 0 9 TXD TXD EasyDMA channel UARTE_TXD read-write 0x544 PTR Data pointer 0x000 read-write PTR Data pointer 0 31 MAXCNT Maximum number of bytes in transmit buffer 0x004 read-write MAXCNT Maximum number of bytes in transmit buffer 0 9 AMOUNT Number of bytes transferred in the last transaction 0x008 read-only AMOUNT Number of bytes transferred in the last transaction 0 9 CONFIG Configuration of parity and hardware flow control 0x56C read-write HWFC Hardware flow control 0 0 Disabled Disabled 0 Enabled Enabled 1 PARITY Parity 1 3 Excluded Exclude parity bit 0x0 Included Include even parity bit 0x7 STOP Stop bits 4 4 One One stop bit 0 Two Two stop bits 1 TWI0 I2C compatible Two-Wire Interface 0x40003000 TWI 0 0x1000 registers TWIM0_TWIS0_TWI0 3 TWI 0x20 TASKS_STARTRX Start TWI receive sequence 0x000 write-only TASKS_STARTRX Start TWI receive sequence 0 0 Trigger Trigger task 1 TASKS_STARTTX Start TWI transmit sequence 0x008 write-only TASKS_STARTTX Start TWI transmit sequence 0 0 Trigger Trigger task 1 TASKS_STOP Stop TWI transaction 0x014 write-only TASKS_STOP Stop TWI transaction 0 0 Trigger Trigger task 1 TASKS_SUSPEND Suspend TWI transaction 0x01C write-only TASKS_SUSPEND Suspend TWI transaction 0 0 Trigger Trigger task 1 TASKS_RESUME Resume TWI transaction 0x020 write-only TASKS_RESUME Resume TWI transaction 0 0 Trigger Trigger task 1 EVENTS_STOPPED TWI stopped 0x104 read-write EVENTS_STOPPED TWI stopped 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_RXDREADY TWI RXD byte received 0x108 read-write EVENTS_RXDREADY TWI RXD byte received 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_TXDSENT TWI TXD byte sent 0x11C read-write EVENTS_TXDSENT TWI TXD byte sent 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_ERROR TWI error 0x124 read-write EVENTS_ERROR TWI error 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_BB TWI byte boundary, generated before each byte that is sent or received 0x138 read-write EVENTS_BB TWI byte boundary, generated before each byte that is sent or received 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_SUSPENDED TWI entered the suspended state 0x148 read-write EVENTS_SUSPENDED TWI entered the suspended state 0 0 NotGenerated Event not generated 0 Generated Event generated 1 SHORTS Shortcuts between local events and tasks 0x200 read-write BB_SUSPEND Shortcut between event BB and task SUSPEND 0 0 Disabled Disable shortcut 0 Enabled Enable shortcut 1 BB_STOP Shortcut between event BB and task STOP 1 1 Disabled Disable shortcut 0 Enabled Enable shortcut 1 INTENSET Enable interrupt 0x304 read-write STOPPED Write '1' to enable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 RXDREADY Write '1' to enable interrupt for event RXDREADY 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TXDSENT Write '1' to enable interrupt for event TXDSENT 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ERROR Write '1' to enable interrupt for event ERROR 9 9 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 BB Write '1' to enable interrupt for event BB 14 14 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 SUSPENDED Write '1' to enable interrupt for event SUSPENDED 18 18 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write STOPPED Write '1' to disable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RXDREADY Write '1' to disable interrupt for event RXDREADY 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TXDSENT Write '1' to disable interrupt for event TXDSENT 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ERROR Write '1' to disable interrupt for event ERROR 9 9 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 BB Write '1' to disable interrupt for event BB 14 14 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 SUSPENDED Write '1' to disable interrupt for event SUSPENDED 18 18 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ERRORSRC Error source 0x4C4 read-write oneToClear OVERRUN Overrun error 0 0 read NotPresent Read: no overrun occured 0 Present Read: overrun occured 1 ANACK NACK received after sending the address (write '1' to clear) 1 1 read NotPresent Read: error not present 0 Present Read: error present 1 DNACK NACK received after sending a data byte (write '1' to clear) 2 2 read NotPresent Read: error not present 0 Present Read: error present 1 ENABLE Enable TWI 0x500 read-write ENABLE Enable or disable TWI 0 3 Disabled Disable TWI 0 Enabled Enable TWI 5 PSEL Unspecified TWI_PSEL read-write 0x508 SCL Pin select for SCL 0x000 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 SDA Pin select for SDA 0x004 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 RXD RXD register 0x518 read-only modifyExternal RXD RXD register 0 7 TXD TXD register 0x51C read-write TXD TXD register 0 7 FREQUENCY TWI frequency. Accuracy depends on the HFCLK source selected. 0x524 read-write 0x04000000 FREQUENCY TWI master clock frequency 0 31 K100 100 kbps 0x01980000 K250 250 kbps 0x04000000 K400 400 kbps (actual rate 410.256 kbps) 0x06680000 ADDRESS Address used in the TWI transfer 0x588 read-write ADDRESS Address used in the TWI transfer 0 6 TWIM0 I2C compatible Two-Wire Master Interface with EasyDMA 0x40003000 TWI0 TWIM 0 0x1000 registers TWIM0_TWIS0_TWI0 3 TWIM 0x20 TASKS_STARTRX Start TWI receive sequence 0x000 write-only TASKS_STARTRX Start TWI receive sequence 0 0 Trigger Trigger task 1 TASKS_STARTTX Start TWI transmit sequence 0x008 write-only TASKS_STARTTX Start TWI transmit sequence 0 0 Trigger Trigger task 1 TASKS_STOP Stop TWI transaction. Must be issued while the TWI master is not suspended. 0x014 write-only TASKS_STOP Stop TWI transaction. Must be issued while the TWI master is not suspended. 0 0 Trigger Trigger task 1 TASKS_SUSPEND Suspend TWI transaction 0x01C write-only TASKS_SUSPEND Suspend TWI transaction 0 0 Trigger Trigger task 1 TASKS_RESUME Resume TWI transaction 0x020 write-only TASKS_RESUME Resume TWI transaction 0 0 Trigger Trigger task 1 EVENTS_STOPPED TWI stopped 0x104 read-write EVENTS_STOPPED TWI stopped 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_ERROR TWI error 0x124 read-write EVENTS_ERROR TWI error 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_SUSPENDED SUSPEND task has been issued, TWI traffic is now suspended. 0x148 read-write EVENTS_SUSPENDED SUSPEND task has been issued, TWI traffic is now suspended. 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_RXSTARTED Receive sequence started 0x14C read-write EVENTS_RXSTARTED Receive sequence started 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_TXSTARTED Transmit sequence started 0x150 read-write EVENTS_TXSTARTED Transmit sequence started 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_LASTRX Byte boundary, starting to receive the last byte 0x15C read-write EVENTS_LASTRX Byte boundary, starting to receive the last byte 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_LASTTX Byte boundary, starting to transmit the last byte 0x160 read-write EVENTS_LASTTX Byte boundary, starting to transmit the last byte 0 0 NotGenerated Event not generated 0 Generated Event generated 1 SHORTS Shortcuts between local events and tasks 0x200 read-write LASTTX_STARTRX Shortcut between event LASTTX and task STARTRX 7 7 Disabled Disable shortcut 0 Enabled Enable shortcut 1 LASTTX_SUSPEND Shortcut between event LASTTX and task SUSPEND 8 8 Disabled Disable shortcut 0 Enabled Enable shortcut 1 LASTTX_STOP Shortcut between event LASTTX and task STOP 9 9 Disabled Disable shortcut 0 Enabled Enable shortcut 1 LASTRX_STARTTX Shortcut between event LASTRX and task STARTTX 10 10 Disabled Disable shortcut 0 Enabled Enable shortcut 1 LASTRX_SUSPEND Shortcut between event LASTRX and task SUSPEND 11 11 Disabled Disable shortcut 0 Enabled Enable shortcut 1 LASTRX_STOP Shortcut between event LASTRX and task STOP 12 12 Disabled Disable shortcut 0 Enabled Enable shortcut 1 INTEN Enable or disable interrupt 0x300 read-write STOPPED Enable or disable interrupt for event STOPPED 1 1 Disabled Disable 0 Enabled Enable 1 ERROR Enable or disable interrupt for event ERROR 9 9 Disabled Disable 0 Enabled Enable 1 SUSPENDED Enable or disable interrupt for event SUSPENDED 18 18 Disabled Disable 0 Enabled Enable 1 RXSTARTED Enable or disable interrupt for event RXSTARTED 19 19 Disabled Disable 0 Enabled Enable 1 TXSTARTED Enable or disable interrupt for event TXSTARTED 20 20 Disabled Disable 0 Enabled Enable 1 LASTRX Enable or disable interrupt for event LASTRX 23 23 Disabled Disable 0 Enabled Enable 1 LASTTX Enable or disable interrupt for event LASTTX 24 24 Disabled Disable 0 Enabled Enable 1 INTENSET Enable interrupt 0x304 read-write STOPPED Write '1' to enable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ERROR Write '1' to enable interrupt for event ERROR 9 9 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 SUSPENDED Write '1' to enable interrupt for event SUSPENDED 18 18 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 RXSTARTED Write '1' to enable interrupt for event RXSTARTED 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TXSTARTED Write '1' to enable interrupt for event TXSTARTED 20 20 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 LASTRX Write '1' to enable interrupt for event LASTRX 23 23 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 LASTTX Write '1' to enable interrupt for event LASTTX 24 24 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write STOPPED Write '1' to disable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ERROR Write '1' to disable interrupt for event ERROR 9 9 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 SUSPENDED Write '1' to disable interrupt for event SUSPENDED 18 18 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RXSTARTED Write '1' to disable interrupt for event RXSTARTED 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TXSTARTED Write '1' to disable interrupt for event TXSTARTED 20 20 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 LASTRX Write '1' to disable interrupt for event LASTRX 23 23 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 LASTTX Write '1' to disable interrupt for event LASTTX 24 24 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ERRORSRC Error source 0x4C4 read-write oneToClear OVERRUN Overrun error 0 0 NotReceived Error did not occur 0 Received Error occurred 1 ANACK NACK received after sending the address (write '1' to clear) 1 1 NotReceived Error did not occur 0 Received Error occurred 1 DNACK NACK received after sending a data byte (write '1' to clear) 2 2 NotReceived Error did not occur 0 Received Error occurred 1 ENABLE Enable TWIM 0x500 read-write ENABLE Enable or disable TWIM 0 3 Disabled Disable TWIM 0 Enabled Enable TWIM 6 PSEL Unspecified TWIM_PSEL read-write 0x508 SCL Pin select for SCL signal 0x000 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 SDA Pin select for SDA signal 0x004 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 FREQUENCY TWI frequency. Accuracy depends on the HFCLK source selected. 0x524 read-write 0x04000000 FREQUENCY TWI master clock frequency 0 31 K100 100 kbps 0x01980000 K250 250 kbps 0x04000000 K400 400 kbps 0x06400000 RXD RXD EasyDMA channel TWIM_RXD read-write 0x534 PTR Data pointer 0x000 read-write PTR Data pointer 0 31 MAXCNT Maximum number of bytes in receive buffer 0x004 read-write MAXCNT Maximum number of bytes in receive buffer 0 13 AMOUNT Number of bytes transferred in the last transaction 0x008 read-only AMOUNT Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. 0 13 LIST EasyDMA list type 0x00C read-write LIST List type 0 2 Disabled Disable EasyDMA list 0 ArrayList Use array list 1 TXD TXD EasyDMA channel TWIM_TXD read-write 0x544 PTR Data pointer 0x000 read-write PTR Data pointer 0 31 MAXCNT Maximum number of bytes in transmit buffer 0x004 read-write MAXCNT Maximum number of bytes in transmit buffer 0 13 AMOUNT Number of bytes transferred in the last transaction 0x008 read-only AMOUNT Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. 0 13 LIST EasyDMA list type 0x00C read-write LIST List type 0 2 Disabled Disable EasyDMA list 0 ArrayList Use array list 1 ADDRESS Address used in the TWI transfer 0x588 read-write ADDRESS Address used in the TWI transfer 0 6 TWIS0 I2C compatible Two-Wire Slave Interface with EasyDMA 0x40003000 TWI0 TWIS 0 0x1000 registers TWIM0_TWIS0_TWI0 3 TWIS 0x20 TASKS_STOP Stop TWI transaction 0x014 write-only TASKS_STOP Stop TWI transaction 0 0 Trigger Trigger task 1 TASKS_SUSPEND Suspend TWI transaction 0x01C write-only TASKS_SUSPEND Suspend TWI transaction 0 0 Trigger Trigger task 1 TASKS_RESUME Resume TWI transaction 0x020 write-only TASKS_RESUME Resume TWI transaction 0 0 Trigger Trigger task 1 TASKS_PREPARERX Prepare the TWI slave to respond to a write command 0x030 write-only TASKS_PREPARERX Prepare the TWI slave to respond to a write command 0 0 Trigger Trigger task 1 TASKS_PREPARETX Prepare the TWI slave to respond to a read command 0x034 write-only TASKS_PREPARETX Prepare the TWI slave to respond to a read command 0 0 Trigger Trigger task 1 EVENTS_STOPPED TWI stopped 0x104 read-write EVENTS_STOPPED TWI stopped 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_ERROR TWI error 0x124 read-write EVENTS_ERROR TWI error 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_RXSTARTED Receive sequence started 0x14C read-write EVENTS_RXSTARTED Receive sequence started 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_TXSTARTED Transmit sequence started 0x150 read-write EVENTS_TXSTARTED Transmit sequence started 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_WRITE Write command received 0x164 read-write EVENTS_WRITE Write command received 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_READ Read command received 0x168 read-write EVENTS_READ Read command received 0 0 NotGenerated Event not generated 0 Generated Event generated 1 SHORTS Shortcuts between local events and tasks 0x200 read-write WRITE_SUSPEND Shortcut between event WRITE and task SUSPEND 13 13 Disabled Disable shortcut 0 Enabled Enable shortcut 1 READ_SUSPEND Shortcut between event READ and task SUSPEND 14 14 Disabled Disable shortcut 0 Enabled Enable shortcut 1 INTEN Enable or disable interrupt 0x300 read-write STOPPED Enable or disable interrupt for event STOPPED 1 1 Disabled Disable 0 Enabled Enable 1 ERROR Enable or disable interrupt for event ERROR 9 9 Disabled Disable 0 Enabled Enable 1 RXSTARTED Enable or disable interrupt for event RXSTARTED 19 19 Disabled Disable 0 Enabled Enable 1 TXSTARTED Enable or disable interrupt for event TXSTARTED 20 20 Disabled Disable 0 Enabled Enable 1 WRITE Enable or disable interrupt for event WRITE 25 25 Disabled Disable 0 Enabled Enable 1 READ Enable or disable interrupt for event READ 26 26 Disabled Disable 0 Enabled Enable 1 INTENSET Enable interrupt 0x304 read-write STOPPED Write '1' to enable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ERROR Write '1' to enable interrupt for event ERROR 9 9 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 RXSTARTED Write '1' to enable interrupt for event RXSTARTED 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TXSTARTED Write '1' to enable interrupt for event TXSTARTED 20 20 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 WRITE Write '1' to enable interrupt for event WRITE 25 25 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 READ Write '1' to enable interrupt for event READ 26 26 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write STOPPED Write '1' to disable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ERROR Write '1' to disable interrupt for event ERROR 9 9 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RXSTARTED Write '1' to disable interrupt for event RXSTARTED 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TXSTARTED Write '1' to disable interrupt for event TXSTARTED 20 20 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 WRITE Write '1' to disable interrupt for event WRITE 25 25 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 READ Write '1' to disable interrupt for event READ 26 26 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ERRORSRC Error source 0x4D0 read-write oneToClear OVERFLOW RX buffer overflow detected, and prevented 0 0 NotDetected Error did not occur 0 Detected Error occurred 1 DNACK NACK sent after receiving a data byte 2 2 NotReceived Error did not occur 0 Received Error occurred 1 OVERREAD TX buffer over-read detected, and prevented 3 3 NotDetected Error did not occur 0 Detected Error occurred 1 MATCH Status register indicating which address had a match 0x4D4 read-only MATCH Indication of which address in {ADDRESS} that matched the incoming address 0 0 ENABLE Enable TWIS 0x500 read-write ENABLE Enable or disable TWIS 0 3 Disabled Disable TWIS 0 Enabled Enable TWIS 9 PSEL Unspecified TWIS_PSEL read-write 0x508 SCL Pin select for SCL signal 0x000 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 SDA Pin select for SDA signal 0x004 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 RXD RXD EasyDMA channel TWIS_RXD read-write 0x534 PTR RXD Data pointer 0x000 read-write PTR RXD Data pointer 0 31 MAXCNT Maximum number of bytes in RXD buffer 0x004 read-write MAXCNT Maximum number of bytes in RXD buffer 0 13 AMOUNT Number of bytes transferred in the last RXD transaction 0x008 read-only AMOUNT Number of bytes transferred in the last RXD transaction 0 13 LIST EasyDMA list type 0x00C read-write LIST List type 0 1 Disabled Disable EasyDMA list 0 ArrayList Use array list 1 TXD TXD EasyDMA channel TWIS_TXD read-write 0x544 PTR TXD Data pointer 0x000 read-write PTR TXD Data pointer 0 31 MAXCNT Maximum number of bytes in TXD buffer 0x004 read-write MAXCNT Maximum number of bytes in TXD buffer 0 13 AMOUNT Number of bytes transferred in the last TXD transaction 0x008 read-only AMOUNT Number of bytes transferred in the last TXD transaction 0 13 LIST EasyDMA list type 0x00C read-write LIST List type 0 1 Disabled Disable EasyDMA list 0 ArrayList Use array list 1 0x2 0x4 ADDRESS[%s] Description collection: TWI slave address n 0x588 read-write ADDRESS TWI slave address 0 6 CONFIG Configuration register for the address match mechanism 0x594 read-write 0x00000001 ADDRESS0 Enable or disable address matching on ADDRESS[0] 0 0 Disabled Disabled 0 Enabled Enabled 1 ADDRESS1 Enable or disable address matching on ADDRESS[1] 1 1 Disabled Disabled 0 Enabled Enabled 1 ORC Over-read character. Character sent out in case of an over-read of the transmit buffer. 0x5C0 read-write ORC Over-read character. Character sent out in case of an over-read of the transmit buffer. 0 7 SPI0 Serial Peripheral Interface 0x40004000 SPI 0 0x1000 registers SPIM0_SPIS0_SPI0 4 SPI 0x20 EVENTS_READY TXD byte sent and RXD byte received 0x108 read-write EVENTS_READY TXD byte sent and RXD byte received 0 0 NotGenerated Event not generated 0 Generated Event generated 1 INTENSET Enable interrupt 0x304 read-write READY Write '1' to enable interrupt for event READY 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write READY Write '1' to disable interrupt for event READY 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENABLE Enable SPI 0x500 read-write ENABLE Enable or disable SPI 0 3 Disabled Disable SPI 0 Enabled Enable SPI 1 PSEL Unspecified SPI_PSEL read-write 0x508 SCK Pin select for SCK 0x000 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 MOSI Pin select for MOSI signal 0x004 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 MISO Pin select for MISO signal 0x008 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 RXD RXD register 0x518 read-only modifyExternal RXD RX data received. Double buffered 0 7 TXD TXD register 0x51C read-write TXD TX data to send. Double buffered. 0 7 FREQUENCY SPI frequency. Accuracy depends on the HFCLK source selected. 0x524 read-write 0x04000000 FREQUENCY SPI master data rate 0 31 K125 125 kbps 0x02000000 K250 250 kbps 0x04000000 K500 500 kbps 0x08000000 M1 1 Mbps 0x10000000 M2 2 Mbps 0x20000000 M4 4 Mbps 0x40000000 M8 8 Mbps 0x80000000 CONFIG Configuration register 0x554 read-write ORDER Bit order 0 0 MsbFirst Most significant bit shifted out first 0 LsbFirst Least significant bit shifted out first 1 CPHA Serial clock (SCK) phase 1 1 Leading Sample on leading edge of clock, shift serial data on trailing edge 0 Trailing Sample on trailing edge of clock, shift serial data on leading edge 1 CPOL Serial clock (SCK) polarity 2 2 ActiveHigh Active high 0 ActiveLow Active low 1 SPIM0 Serial Peripheral Interface Master with EasyDMA 0x40004000 SPI0 SPIM 0 0x1000 registers SPIM0_SPIS0_SPI0 4 SPIM 0x20 TASKS_START Start SPI transaction 0x010 write-only TASKS_START Start SPI transaction 0 0 Trigger Trigger task 1 TASKS_STOP Stop SPI transaction 0x014 write-only TASKS_STOP Stop SPI transaction 0 0 Trigger Trigger task 1 TASKS_SUSPEND Suspend SPI transaction 0x01C write-only TASKS_SUSPEND Suspend SPI transaction 0 0 Trigger Trigger task 1 TASKS_RESUME Resume SPI transaction 0x020 write-only TASKS_RESUME Resume SPI transaction 0 0 Trigger Trigger task 1 EVENTS_STOPPED SPI transaction has stopped 0x104 read-write EVENTS_STOPPED SPI transaction has stopped 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_ENDRX End of RXD buffer reached 0x110 read-write EVENTS_ENDRX End of RXD buffer reached 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_END End of RXD buffer and TXD buffer reached 0x118 read-write EVENTS_END End of RXD buffer and TXD buffer reached 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_ENDTX End of TXD buffer reached 0x120 read-write EVENTS_ENDTX End of TXD buffer reached 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_STARTED Transaction started 0x14C read-write EVENTS_STARTED Transaction started 0 0 NotGenerated Event not generated 0 Generated Event generated 1 SHORTS Shortcuts between local events and tasks 0x200 read-write END_START Shortcut between event END and task START 17 17 Disabled Disable shortcut 0 Enabled Enable shortcut 1 INTENSET Enable interrupt 0x304 read-write STOPPED Write '1' to enable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ENDRX Write '1' to enable interrupt for event ENDRX 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 END Write '1' to enable interrupt for event END 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ENDTX Write '1' to enable interrupt for event ENDTX 8 8 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 STARTED Write '1' to enable interrupt for event STARTED 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write STOPPED Write '1' to disable interrupt for event STOPPED 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENDRX Write '1' to disable interrupt for event ENDRX 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 END Write '1' to disable interrupt for event END 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENDTX Write '1' to disable interrupt for event ENDTX 8 8 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 STARTED Write '1' to disable interrupt for event STARTED 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENABLE Enable SPIM 0x500 read-write ENABLE Enable or disable SPIM 0 3 Disabled Disable SPIM 0 Enabled Enable SPIM 7 PSEL Unspecified SPIM_PSEL read-write 0x508 SCK Pin select for SCK 0x000 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 MOSI Pin select for MOSI signal 0x004 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 MISO Pin select for MISO signal 0x008 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 FREQUENCY SPI frequency. Accuracy depends on the HFCLK source selected. 0x524 read-write 0x04000000 FREQUENCY SPI master data rate 0 31 K125 125 kbps 0x02000000 K250 250 kbps 0x04000000 K500 500 kbps 0x08000000 M1 1 Mbps 0x10000000 M2 2 Mbps 0x20000000 M4 4 Mbps 0x40000000 M8 8 Mbps 0x80000000 RXD RXD EasyDMA channel SPIM_RXD read-write 0x534 PTR Data pointer 0x000 read-write PTR Data pointer 0 31 MAXCNT Maximum number of bytes in receive buffer 0x004 read-write MAXCNT Maximum number of bytes in receive buffer 0 13 AMOUNT Number of bytes transferred in the last transaction 0x008 read-only AMOUNT Number of bytes transferred in the last transaction 0 13 LIST EasyDMA list type 0x00C read-write LIST List type 0 1 Disabled Disable EasyDMA list 0 ArrayList Use array list 1 TXD TXD EasyDMA channel SPIM_TXD read-write 0x544 PTR Data pointer 0x000 read-write PTR Data pointer 0 31 MAXCNT Maximum number of bytes in transmit buffer 0x004 read-write MAXCNT Maximum number of bytes in transmit buffer 0 13 AMOUNT Number of bytes transferred in the last transaction 0x008 read-only AMOUNT Number of bytes transferred in the last transaction 0 13 LIST EasyDMA list type 0x00C read-write LIST List type 0 1 Disabled Disable EasyDMA list 0 ArrayList Use array list 1 CONFIG Configuration register 0x554 read-write ORDER Bit order 0 0 MsbFirst Most significant bit shifted out first 0 LsbFirst Least significant bit shifted out first 1 CPHA Serial clock (SCK) phase 1 1 Leading Sample on leading edge of clock, shift serial data on trailing edge 0 Trailing Sample on trailing edge of clock, shift serial data on leading edge 1 CPOL Serial clock (SCK) polarity 2 2 ActiveHigh Active high 0 ActiveLow Active low 1 ORC Over-read character. Character clocked out in case and over-read of the TXD buffer. 0x5C0 read-write ORC Over-read character. Character clocked out in case and over-read of the TXD buffer. 0 7 SPIS0 SPI Slave 0x40004000 SPI0 SPIS 0 0x1000 registers SPIM0_SPIS0_SPI0 4 SPIS 0x20 TASKS_ACQUIRE Acquire SPI semaphore 0x024 write-only TASKS_ACQUIRE Acquire SPI semaphore 0 0 Trigger Trigger task 1 TASKS_RELEASE Release SPI semaphore, enabling the SPI slave to acquire it 0x028 write-only TASKS_RELEASE Release SPI semaphore, enabling the SPI slave to acquire it 0 0 Trigger Trigger task 1 EVENTS_END Granted transaction completed 0x104 read-write EVENTS_END Granted transaction completed 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_ENDRX End of RXD buffer reached 0x110 read-write EVENTS_ENDRX End of RXD buffer reached 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_ACQUIRED Semaphore acquired 0x128 read-write EVENTS_ACQUIRED Semaphore acquired 0 0 NotGenerated Event not generated 0 Generated Event generated 1 SHORTS Shortcuts between local events and tasks 0x200 read-write END_ACQUIRE Shortcut between event END and task ACQUIRE 2 2 Disabled Disable shortcut 0 Enabled Enable shortcut 1 INTENSET Enable interrupt 0x304 read-write END Write '1' to enable interrupt for event END 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ENDRX Write '1' to enable interrupt for event ENDRX 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ACQUIRED Write '1' to enable interrupt for event ACQUIRED 10 10 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write END Write '1' to disable interrupt for event END 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENDRX Write '1' to disable interrupt for event ENDRX 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ACQUIRED Write '1' to disable interrupt for event ACQUIRED 10 10 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 SEMSTAT Semaphore status register 0x400 read-only 0x00000001 SEMSTAT Semaphore status 0 1 Free Semaphore is free 0 CPU Semaphore is assigned to CPU 1 SPIS Semaphore is assigned to SPI slave 2 CPUPending Semaphore is assigned to SPI but a handover to the CPU is pending 3 STATUS Status from last transaction 0x440 read-write OVERREAD TX buffer over-read detected, and prevented 0 0 read NotPresent Read: error not present 0 Present Read: error present 1 write Clear Write: clear error on writing '1' 1 OVERFLOW RX buffer overflow detected, and prevented 1 1 read NotPresent Read: error not present 0 Present Read: error present 1 write Clear Write: clear error on writing '1' 1 ENABLE Enable SPI slave 0x500 read-write ENABLE Enable or disable SPI slave 0 3 Disabled Disable SPI slave 0 Enabled Enable SPI slave 2 PSEL Unspecified SPIS_PSEL read-write 0x508 SCK Pin select for SCK 0x000 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 MISO Pin select for MISO signal 0x004 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 MOSI Pin select for MOSI signal 0x008 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 CSN Pin select for CSN signal 0x00C read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 RXD Unspecified SPIS_RXD read-write 0x534 PTR RXD data pointer 0x000 read-write PTR RXD data pointer 0 31 MAXCNT Maximum number of bytes in receive buffer 0x004 read-write MAXCNT Maximum number of bytes in receive buffer 0 13 AMOUNT Number of bytes received in last granted transaction 0x008 read-only AMOUNT Number of bytes received in the last granted transaction 0 13 LIST EasyDMA list type 0x00C read-write LIST List type 0 1 Disabled Disable EasyDMA list 0 ArrayList Use array list 1 TXD Unspecified SPIS_TXD read-write 0x544 PTR TXD data pointer 0x000 read-write PTR TXD data pointer 0 31 MAXCNT Maximum number of bytes in transmit buffer 0x004 read-write MAXCNT Maximum number of bytes in transmit buffer 0 13 AMOUNT Number of bytes transmitted in last granted transaction 0x008 read-only AMOUNT Number of bytes transmitted in last granted transaction 0 13 LIST EasyDMA list type 0x00C read-write LIST List type 0 1 Disabled Disable EasyDMA list 0 ArrayList Use array list 1 CONFIG Configuration register 0x554 read-write ORDER Bit order 0 0 MsbFirst Most significant bit shifted out first 0 LsbFirst Least significant bit shifted out first 1 CPHA Serial clock (SCK) phase 1 1 Leading Sample on leading edge of clock, shift serial data on trailing edge 0 Trailing Sample on trailing edge of clock, shift serial data on leading edge 1 CPOL Serial clock (SCK) polarity 2 2 ActiveHigh Active high 0 ActiveLow Active low 1 DEF Default character. Character clocked out in case of an ignored transaction. 0x55C read-write DEF Default character. Character clocked out in case of an ignored transaction. 0 7 ORC Over-read character 0x5C0 read-write ORC Over-read character. Character clocked out after an over-read of the transmit buffer. 0 7 GPIOTE GPIO Tasks and Events 0x40006000 0 0x1000 registers GPIOTE 6 GPIOTE 0x20 0x8 0x4 TASKS_OUT[%s] Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. 0x000 write-only TASKS_OUT Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. 0 0 Trigger Trigger task 1 0x8 0x4 TASKS_SET[%s] Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. 0x030 write-only TASKS_SET Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. 0 0 Trigger Trigger task 1 0x8 0x4 TASKS_CLR[%s] Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. 0x060 write-only TASKS_CLR Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. 0 0 Trigger Trigger task 1 0x8 0x4 EVENTS_IN[%s] Description collection: Event generated from pin specified in CONFIG[n].PSEL 0x100 read-write EVENTS_IN Event generated from pin specified in CONFIG[n].PSEL 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_PORT Event generated from multiple input GPIO pins with SENSE mechanism enabled 0x17C read-write EVENTS_PORT Event generated from multiple input GPIO pins with SENSE mechanism enabled 0 0 NotGenerated Event not generated 0 Generated Event generated 1 INTENSET Enable interrupt 0x304 read-write IN0 Write '1' to enable interrupt for event IN[0] 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 IN1 Write '1' to enable interrupt for event IN[1] 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 IN2 Write '1' to enable interrupt for event IN[2] 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 IN3 Write '1' to enable interrupt for event IN[3] 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 IN4 Write '1' to enable interrupt for event IN[4] 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 IN5 Write '1' to enable interrupt for event IN[5] 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 IN6 Write '1' to enable interrupt for event IN[6] 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 IN7 Write '1' to enable interrupt for event IN[7] 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 PORT Write '1' to enable interrupt for event PORT 31 31 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write IN0 Write '1' to disable interrupt for event IN[0] 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 IN1 Write '1' to disable interrupt for event IN[1] 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 IN2 Write '1' to disable interrupt for event IN[2] 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 IN3 Write '1' to disable interrupt for event IN[3] 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 IN4 Write '1' to disable interrupt for event IN[4] 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 IN5 Write '1' to disable interrupt for event IN[5] 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 IN6 Write '1' to disable interrupt for event IN[6] 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 IN7 Write '1' to disable interrupt for event IN[7] 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 PORT Write '1' to disable interrupt for event PORT 31 31 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 0x8 0x4 CONFIG[%s] Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event 0x510 read-write MODE Mode 0 1 Disabled Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. 0 Event Event mode 1 Task Task mode 3 PSEL GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event 8 12 POLARITY When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. 16 17 None Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. 0 LoToHi Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. 1 HiToLo Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. 2 Toggle Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. 3 OUTINIT When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. 20 20 Low Task mode: Initial value of pin before task triggering is low 0 High Task mode: Initial value of pin before task triggering is high 1 SAADC Analog to Digital Converter 0x40007000 0 0x1000 registers SAADC 7 SAADC 0x20 TASKS_START Start the ADC and prepare the result buffer in RAM 0x000 write-only TASKS_START Start the ADC and prepare the result buffer in RAM 0 0 Trigger Trigger task 1 TASKS_SAMPLE Take one ADC sample, if scan is enabled all channels are sampled 0x004 write-only TASKS_SAMPLE Take one ADC sample, if scan is enabled all channels are sampled 0 0 Trigger Trigger task 1 TASKS_STOP Stop the ADC and terminate any on-going conversion 0x008 write-only TASKS_STOP Stop the ADC and terminate any on-going conversion 0 0 Trigger Trigger task 1 TASKS_CALIBRATEOFFSET Starts offset auto-calibration 0x00C write-only TASKS_CALIBRATEOFFSET Starts offset auto-calibration 0 0 Trigger Trigger task 1 EVENTS_STARTED The ADC has started 0x100 read-write EVENTS_STARTED The ADC has started 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_END The ADC has filled up the Result buffer 0x104 read-write EVENTS_END The ADC has filled up the Result buffer 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_DONE A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. 0x108 read-write EVENTS_DONE A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_RESULTDONE A result is ready to get transferred to RAM. 0x10C read-write EVENTS_RESULTDONE A result is ready to get transferred to RAM. 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_CALIBRATEDONE Calibration is complete 0x110 read-write EVENTS_CALIBRATEDONE Calibration is complete 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_STOPPED The ADC has stopped 0x114 read-write EVENTS_STOPPED The ADC has stopped 0 0 NotGenerated Event not generated 0 Generated Event generated 1 8 0x008 EVENTS_CH[%s] Peripheral events. SAADC_EVENTS_CH read-write 0x118 LIMITH Description cluster: Last results is equal or above CH[n].LIMIT.HIGH 0x000 read-write LIMITH Last results is equal or above CH[n].LIMIT.HIGH 0 0 NotGenerated Event not generated 0 Generated Event generated 1 LIMITL Description cluster: Last results is equal or below CH[n].LIMIT.LOW 0x004 read-write LIMITL Last results is equal or below CH[n].LIMIT.LOW 0 0 NotGenerated Event not generated 0 Generated Event generated 1 INTEN Enable or disable interrupt 0x300 read-write STARTED Enable or disable interrupt for event STARTED 0 0 Disabled Disable 0 Enabled Enable 1 END Enable or disable interrupt for event END 1 1 Disabled Disable 0 Enabled Enable 1 DONE Enable or disable interrupt for event DONE 2 2 Disabled Disable 0 Enabled Enable 1 RESULTDONE Enable or disable interrupt for event RESULTDONE 3 3 Disabled Disable 0 Enabled Enable 1 CALIBRATEDONE Enable or disable interrupt for event CALIBRATEDONE 4 4 Disabled Disable 0 Enabled Enable 1 STOPPED Enable or disable interrupt for event STOPPED 5 5 Disabled Disable 0 Enabled Enable 1 CH0LIMITH Enable or disable interrupt for event CH0LIMITH 6 6 Disabled Disable 0 Enabled Enable 1 CH0LIMITL Enable or disable interrupt for event CH0LIMITL 7 7 Disabled Disable 0 Enabled Enable 1 CH1LIMITH Enable or disable interrupt for event CH1LIMITH 8 8 Disabled Disable 0 Enabled Enable 1 CH1LIMITL Enable or disable interrupt for event CH1LIMITL 9 9 Disabled Disable 0 Enabled Enable 1 CH2LIMITH Enable or disable interrupt for event CH2LIMITH 10 10 Disabled Disable 0 Enabled Enable 1 CH2LIMITL Enable or disable interrupt for event CH2LIMITL 11 11 Disabled Disable 0 Enabled Enable 1 CH3LIMITH Enable or disable interrupt for event CH3LIMITH 12 12 Disabled Disable 0 Enabled Enable 1 CH3LIMITL Enable or disable interrupt for event CH3LIMITL 13 13 Disabled Disable 0 Enabled Enable 1 CH4LIMITH Enable or disable interrupt for event CH4LIMITH 14 14 Disabled Disable 0 Enabled Enable 1 CH4LIMITL Enable or disable interrupt for event CH4LIMITL 15 15 Disabled Disable 0 Enabled Enable 1 CH5LIMITH Enable or disable interrupt for event CH5LIMITH 16 16 Disabled Disable 0 Enabled Enable 1 CH5LIMITL Enable or disable interrupt for event CH5LIMITL 17 17 Disabled Disable 0 Enabled Enable 1 CH6LIMITH Enable or disable interrupt for event CH6LIMITH 18 18 Disabled Disable 0 Enabled Enable 1 CH6LIMITL Enable or disable interrupt for event CH6LIMITL 19 19 Disabled Disable 0 Enabled Enable 1 CH7LIMITH Enable or disable interrupt for event CH7LIMITH 20 20 Disabled Disable 0 Enabled Enable 1 CH7LIMITL Enable or disable interrupt for event CH7LIMITL 21 21 Disabled Disable 0 Enabled Enable 1 INTENSET Enable interrupt 0x304 read-write STARTED Write '1' to enable interrupt for event STARTED 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 END Write '1' to enable interrupt for event END 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 DONE Write '1' to enable interrupt for event DONE 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 RESULTDONE Write '1' to enable interrupt for event RESULTDONE 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CALIBRATEDONE Write '1' to enable interrupt for event CALIBRATEDONE 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 STOPPED Write '1' to enable interrupt for event STOPPED 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH0LIMITH Write '1' to enable interrupt for event CH0LIMITH 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH0LIMITL Write '1' to enable interrupt for event CH0LIMITL 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH1LIMITH Write '1' to enable interrupt for event CH1LIMITH 8 8 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH1LIMITL Write '1' to enable interrupt for event CH1LIMITL 9 9 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH2LIMITH Write '1' to enable interrupt for event CH2LIMITH 10 10 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH2LIMITL Write '1' to enable interrupt for event CH2LIMITL 11 11 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH3LIMITH Write '1' to enable interrupt for event CH3LIMITH 12 12 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH3LIMITL Write '1' to enable interrupt for event CH3LIMITL 13 13 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH4LIMITH Write '1' to enable interrupt for event CH4LIMITH 14 14 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH4LIMITL Write '1' to enable interrupt for event CH4LIMITL 15 15 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH5LIMITH Write '1' to enable interrupt for event CH5LIMITH 16 16 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH5LIMITL Write '1' to enable interrupt for event CH5LIMITL 17 17 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH6LIMITH Write '1' to enable interrupt for event CH6LIMITH 18 18 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH6LIMITL Write '1' to enable interrupt for event CH6LIMITL 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH7LIMITH Write '1' to enable interrupt for event CH7LIMITH 20 20 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH7LIMITL Write '1' to enable interrupt for event CH7LIMITL 21 21 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write STARTED Write '1' to disable interrupt for event STARTED 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 END Write '1' to disable interrupt for event END 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 DONE Write '1' to disable interrupt for event DONE 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RESULTDONE Write '1' to disable interrupt for event RESULTDONE 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CALIBRATEDONE Write '1' to disable interrupt for event CALIBRATEDONE 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 STOPPED Write '1' to disable interrupt for event STOPPED 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH0LIMITH Write '1' to disable interrupt for event CH0LIMITH 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH0LIMITL Write '1' to disable interrupt for event CH0LIMITL 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH1LIMITH Write '1' to disable interrupt for event CH1LIMITH 8 8 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH1LIMITL Write '1' to disable interrupt for event CH1LIMITL 9 9 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH2LIMITH Write '1' to disable interrupt for event CH2LIMITH 10 10 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH2LIMITL Write '1' to disable interrupt for event CH2LIMITL 11 11 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH3LIMITH Write '1' to disable interrupt for event CH3LIMITH 12 12 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH3LIMITL Write '1' to disable interrupt for event CH3LIMITL 13 13 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH4LIMITH Write '1' to disable interrupt for event CH4LIMITH 14 14 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH4LIMITL Write '1' to disable interrupt for event CH4LIMITL 15 15 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH5LIMITH Write '1' to disable interrupt for event CH5LIMITH 16 16 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH5LIMITL Write '1' to disable interrupt for event CH5LIMITL 17 17 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH6LIMITH Write '1' to disable interrupt for event CH6LIMITH 18 18 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH6LIMITL Write '1' to disable interrupt for event CH6LIMITL 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH7LIMITH Write '1' to disable interrupt for event CH7LIMITH 20 20 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH7LIMITL Write '1' to disable interrupt for event CH7LIMITL 21 21 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 STATUS Status 0x400 read-only STATUS Status 0 0 Ready ADC is ready. No on-going conversion. 0 Busy ADC is busy. Conversion in progress. 1 ENABLE Enable or disable ADC 0x500 read-write ENABLE Enable or disable ADC 0 0 Disabled Disable ADC 0 Enabled Enable ADC 1 8 0x010 CH[%s] Unspecified SAADC_CH read-write 0x510 PSELP Description cluster: Input positive pin selection for CH[n] 0x000 read-write 0x00000000 PSELP Analog positive input channel 0 4 NC Not connected 0 AnalogInput0 AIN0 1 AnalogInput1 AIN1 2 AnalogInput2 AIN2 3 AnalogInput3 AIN3 4 AnalogInput4 AIN4 5 AnalogInput5 AIN5 6 AnalogInput6 AIN6 7 AnalogInput7 AIN7 8 VDD VDD 9 PSELN Description cluster: Input negative pin selection for CH[n] 0x004 read-write 0x00000000 PSELN Analog negative input, enables differential channel 0 4 NC Not connected 0 AnalogInput0 AIN0 1 AnalogInput1 AIN1 2 AnalogInput2 AIN2 3 AnalogInput3 AIN3 4 AnalogInput4 AIN4 5 AnalogInput5 AIN5 6 AnalogInput6 AIN6 7 AnalogInput7 AIN7 8 VDD VDD 9 CONFIG Description cluster: Input configuration for CH[n] 0x008 read-write 0x00020000 RESP Positive channel resistor control 0 1 Bypass Bypass resistor ladder 0 Pulldown Pull-down to GND 1 Pullup Pull-up to VDD 2 VDD1_2 Set input at VDD/2 3 RESN Negative channel resistor control 4 5 Bypass Bypass resistor ladder 0 Pulldown Pull-down to GND 1 Pullup Pull-up to VDD 2 VDD1_2 Set input at VDD/2 3 GAIN Gain control 8 10 Gain1_6 1/6 0 Gain1_5 1/5 1 Gain1_4 1/4 2 Gain1_3 1/3 3 Gain1_2 1/2 4 Gain1 1 5 Gain2 2 6 Gain4 4 7 REFSEL Reference control 12 12 Internal Internal reference (0.6 V) 0 VDD1_4 VDD/4 as reference 1 TACQ Acquisition time, the time the ADC uses to sample the input voltage 16 18 3us 3 us 0 5us 5 us 1 10us 10 us 2 15us 15 us 3 20us 20 us 4 40us 40 us 5 MODE Enable differential mode 20 20 SE Single ended, PSELN will be ignored, negative input to ADC shorted to GND 0 Diff Differential 1 BURST Enable burst mode 24 24 Disabled Burst mode is disabled (normal operation) 0 Enabled Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. 1 LIMIT Description cluster: High/low limits for event monitoring a channel 0x00C read-write 0x7FFF8000 LOW Low level limit 0 15 HIGH High level limit 16 31 RESOLUTION Resolution configuration 0x5F0 read-write 0x00000001 VAL Set the resolution 0 2 8bit 8 bit 0 10bit 10 bit 1 12bit 12 bit 2 14bit 14 bit 3 OVERSAMPLE Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. 0x5F4 read-write OVERSAMPLE Oversample control 0 3 Bypass Bypass oversampling 0 Over2x Oversample 2x 1 Over4x Oversample 4x 2 Over8x Oversample 8x 3 Over16x Oversample 16x 4 Over32x Oversample 32x 5 Over64x Oversample 64x 6 Over128x Oversample 128x 7 Over256x Oversample 256x 8 SAMPLERATE Controls normal or continuous sample rate 0x5F8 read-write CC Capture and compare value. Sample rate is 16 MHz/CC 0 10 MODE Select mode for sample rate control 12 12 Task Rate is controlled from SAMPLE task 0 Timers Rate is controlled from local timer (use CC to control the rate) 1 RESULT RESULT EasyDMA channel SAADC_RESULT read-write 0x62C PTR Data pointer 0x000 read-write PTR Data pointer 0 31 MAXCNT Maximum number of buffer words to transfer 0x004 read-write MAXCNT Maximum number of buffer words to transfer 0 14 AMOUNT Number of buffer words transferred since last START 0x008 read-only AMOUNT Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. 0 14 TIMER0 Timer/Counter 0 0x40008000 TIMER 0 0x1000 registers TIMER0 8 TIMER 0x20 TASKS_START Start Timer 0x000 write-only TASKS_START Start Timer 0 0 Trigger Trigger task 1 TASKS_STOP Stop Timer 0x004 write-only TASKS_STOP Stop Timer 0 0 Trigger Trigger task 1 TASKS_COUNT Increment Timer (Counter mode only) 0x008 write-only TASKS_COUNT Increment Timer (Counter mode only) 0 0 Trigger Trigger task 1 TASKS_CLEAR Clear time 0x00C write-only TASKS_CLEAR Clear time 0 0 Trigger Trigger task 1 TASKS_SHUTDOWN Deprecated register - Shut down timer 0x010 write-only TASKS_SHUTDOWN Deprecated field - Shut down timer 0 0 Trigger Trigger task 1 0x6 0x4 TASKS_CAPTURE[%s] Description collection: Capture Timer value to CC[n] register 0x040 write-only TASKS_CAPTURE Capture Timer value to CC[n] register 0 0 Trigger Trigger task 1 0x6 0x4 EVENTS_COMPARE[%s] Description collection: Compare event on CC[n] match 0x140 read-write EVENTS_COMPARE Compare event on CC[n] match 0 0 NotGenerated Event not generated 0 Generated Event generated 1 SHORTS Shortcuts between local events and tasks 0x200 read-write COMPARE0_CLEAR Shortcut between event COMPARE[0] and task CLEAR 0 0 Disabled Disable shortcut 0 Enabled Enable shortcut 1 COMPARE1_CLEAR Shortcut between event COMPARE[1] and task CLEAR 1 1 Disabled Disable shortcut 0 Enabled Enable shortcut 1 COMPARE2_CLEAR Shortcut between event COMPARE[2] and task CLEAR 2 2 Disabled Disable shortcut 0 Enabled Enable shortcut 1 COMPARE3_CLEAR Shortcut between event COMPARE[3] and task CLEAR 3 3 Disabled Disable shortcut 0 Enabled Enable shortcut 1 COMPARE4_CLEAR Shortcut between event COMPARE[4] and task CLEAR 4 4 Disabled Disable shortcut 0 Enabled Enable shortcut 1 COMPARE5_CLEAR Shortcut between event COMPARE[5] and task CLEAR 5 5 Disabled Disable shortcut 0 Enabled Enable shortcut 1 COMPARE0_STOP Shortcut between event COMPARE[0] and task STOP 8 8 Disabled Disable shortcut 0 Enabled Enable shortcut 1 COMPARE1_STOP Shortcut between event COMPARE[1] and task STOP 9 9 Disabled Disable shortcut 0 Enabled Enable shortcut 1 COMPARE2_STOP Shortcut between event COMPARE[2] and task STOP 10 10 Disabled Disable shortcut 0 Enabled Enable shortcut 1 COMPARE3_STOP Shortcut between event COMPARE[3] and task STOP 11 11 Disabled Disable shortcut 0 Enabled Enable shortcut 1 COMPARE4_STOP Shortcut between event COMPARE[4] and task STOP 12 12 Disabled Disable shortcut 0 Enabled Enable shortcut 1 COMPARE5_STOP Shortcut between event COMPARE[5] and task STOP 13 13 Disabled Disable shortcut 0 Enabled Enable shortcut 1 INTENSET Enable interrupt 0x304 read-write COMPARE0 Write '1' to enable interrupt for event COMPARE[0] 16 16 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 COMPARE1 Write '1' to enable interrupt for event COMPARE[1] 17 17 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 COMPARE2 Write '1' to enable interrupt for event COMPARE[2] 18 18 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 COMPARE3 Write '1' to enable interrupt for event COMPARE[3] 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 COMPARE4 Write '1' to enable interrupt for event COMPARE[4] 20 20 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 COMPARE5 Write '1' to enable interrupt for event COMPARE[5] 21 21 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write COMPARE0 Write '1' to disable interrupt for event COMPARE[0] 16 16 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 COMPARE1 Write '1' to disable interrupt for event COMPARE[1] 17 17 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 COMPARE2 Write '1' to disable interrupt for event COMPARE[2] 18 18 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 COMPARE3 Write '1' to disable interrupt for event COMPARE[3] 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 COMPARE4 Write '1' to disable interrupt for event COMPARE[4] 20 20 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 COMPARE5 Write '1' to disable interrupt for event COMPARE[5] 21 21 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 MODE Timer mode selection 0x504 read-write MODE Timer mode 0 1 Timer Select Timer mode 0 Counter Deprecated enumerator - Select Counter mode 1 LowPowerCounter Select Low Power Counter mode 2 BITMODE Configure the number of bits used by the TIMER 0x508 read-write BITMODE Timer bit width 0 1 16Bit 16 bit timer bit width 0 08Bit 8 bit timer bit width 1 24Bit 24 bit timer bit width 2 32Bit 32 bit timer bit width 3 PRESCALER Timer prescaler register 0x510 read-write 0x00000004 PRESCALER Prescaler value 0 3 0x6 0x4 CC[%s] Description collection: Capture/Compare register n 0x540 read-write CC Capture/Compare value 0 31 TIMER1 Timer/Counter 1 0x40009000 TIMER1 9 TIMER2 Timer/Counter 2 0x4000A000 TIMER2 10 RTC0 Real time counter 0 0x4000B000 RTC 0 0x1000 registers RTC0 11 RTC 0x20 TASKS_START Start RTC COUNTER 0x000 write-only TASKS_START Start RTC COUNTER 0 0 Trigger Trigger task 1 TASKS_STOP Stop RTC COUNTER 0x004 write-only TASKS_STOP Stop RTC COUNTER 0 0 Trigger Trigger task 1 TASKS_CLEAR Clear RTC COUNTER 0x008 write-only TASKS_CLEAR Clear RTC COUNTER 0 0 Trigger Trigger task 1 TASKS_TRIGOVRFLW Set COUNTER to 0xFFFFF0 0x00C write-only TASKS_TRIGOVRFLW Set COUNTER to 0xFFFFF0 0 0 Trigger Trigger task 1 EVENTS_TICK Event on COUNTER increment 0x100 read-write EVENTS_TICK Event on COUNTER increment 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_OVRFLW Event on COUNTER overflow 0x104 read-write EVENTS_OVRFLW Event on COUNTER overflow 0 0 NotGenerated Event not generated 0 Generated Event generated 1 0x4 0x4 EVENTS_COMPARE[%s] Description collection: Compare event on CC[n] match 0x140 read-write EVENTS_COMPARE Compare event on CC[n] match 0 0 NotGenerated Event not generated 0 Generated Event generated 1 INTENSET Enable interrupt 0x304 read-write TICK Write '1' to enable interrupt for event TICK 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 OVRFLW Write '1' to enable interrupt for event OVRFLW 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 COMPARE0 Write '1' to enable interrupt for event COMPARE[0] 16 16 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 COMPARE1 Write '1' to enable interrupt for event COMPARE[1] 17 17 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 COMPARE2 Write '1' to enable interrupt for event COMPARE[2] 18 18 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 COMPARE3 Write '1' to enable interrupt for event COMPARE[3] 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write TICK Write '1' to disable interrupt for event TICK 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 OVRFLW Write '1' to disable interrupt for event OVRFLW 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 COMPARE0 Write '1' to disable interrupt for event COMPARE[0] 16 16 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 COMPARE1 Write '1' to disable interrupt for event COMPARE[1] 17 17 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 COMPARE2 Write '1' to disable interrupt for event COMPARE[2] 18 18 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 COMPARE3 Write '1' to disable interrupt for event COMPARE[3] 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 EVTEN Enable or disable event routing 0x340 read-write TICK Enable or disable event routing for event TICK 0 0 Disabled Disable 0 Enabled Disable 1 OVRFLW Enable or disable event routing for event OVRFLW 1 1 Disabled Disable 0 Enabled Disable 1 COMPARE0 Enable or disable event routing for event COMPARE[0] 16 16 Disabled Disable 0 Enabled Disable 1 COMPARE1 Enable or disable event routing for event COMPARE[1] 17 17 Disabled Disable 0 Enabled Disable 1 COMPARE2 Enable or disable event routing for event COMPARE[2] 18 18 Disabled Disable 0 Enabled Disable 1 COMPARE3 Enable or disable event routing for event COMPARE[3] 19 19 Disabled Disable 0 Enabled Disable 1 EVTENSET Enable event routing 0x344 read-write TICK Write '1' to enable event routing for event TICK 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 OVRFLW Write '1' to enable event routing for event OVRFLW 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 COMPARE0 Write '1' to enable event routing for event COMPARE[0] 16 16 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 COMPARE1 Write '1' to enable event routing for event COMPARE[1] 17 17 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 COMPARE2 Write '1' to enable event routing for event COMPARE[2] 18 18 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 COMPARE3 Write '1' to enable event routing for event COMPARE[3] 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 EVTENCLR Disable event routing 0x348 read-write TICK Write '1' to disable event routing for event TICK 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 OVRFLW Write '1' to disable event routing for event OVRFLW 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 COMPARE0 Write '1' to disable event routing for event COMPARE[0] 16 16 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 COMPARE1 Write '1' to disable event routing for event COMPARE[1] 17 17 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 COMPARE2 Write '1' to disable event routing for event COMPARE[2] 18 18 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 COMPARE3 Write '1' to disable event routing for event COMPARE[3] 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 COUNTER Current COUNTER value 0x504 read-only COUNTER Counter value 0 23 PRESCALER 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped 0x508 read-write PRESCALER Prescaler value 0 11 0x4 0x4 CC[%s] Description collection: Compare register n 0x540 read-write COMPARE Compare value 0 23 TEMP Temperature Sensor 0x4000C000 0 0x1000 registers TEMP 12 TEMP 0x20 TASKS_START Start temperature measurement 0x000 write-only TASKS_START Start temperature measurement 0 0 Trigger Trigger task 1 TASKS_STOP Stop temperature measurement 0x004 write-only TASKS_STOP Stop temperature measurement 0 0 Trigger Trigger task 1 EVENTS_DATARDY Temperature measurement complete, data ready 0x100 read-write EVENTS_DATARDY Temperature measurement complete, data ready 0 0 NotGenerated Event not generated 0 Generated Event generated 1 INTENSET Enable interrupt 0x304 read-write DATARDY Write '1' to enable interrupt for event DATARDY 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write DATARDY Write '1' to disable interrupt for event DATARDY 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TEMP Temperature in degC (0.25deg steps) 0x508 read-only int32_t TEMP Temperature in degC (0.25deg steps) 0 31 A0 Slope of first piecewise linear function 0x520 read-write 0x00000326 A0 Slope of first piecewise linear function 0 11 A1 Slope of second piecewise linear function 0x524 read-write 0x00000348 A1 Slope of second piecewise linear function 0 11 A2 Slope of third piecewise linear function 0x528 read-write 0x000003AA A2 Slope of third piecewise linear function 0 11 A3 Slope of fourth piecewise linear function 0x52C read-write 0x0000040E A3 Slope of fourth piecewise linear function 0 11 A4 Slope of fifth piecewise linear function 0x530 read-write 0x000004BD A4 Slope of fifth piecewise linear function 0 11 A5 Slope of sixth piecewise linear function 0x534 read-write 0x000005A3 A5 Slope of sixth piecewise linear function 0 11 B0 y-intercept of first piecewise linear function 0x540 read-write 0x00003FEF B0 y-intercept of first piecewise linear function 0 13 B1 y-intercept of second piecewise linear function 0x544 read-write 0x00003FBE B1 y-intercept of second piecewise linear function 0 13 B2 y-intercept of third piecewise linear function 0x548 read-write 0x00003FBE B2 y-intercept of third piecewise linear function 0 13 B3 y-intercept of fourth piecewise linear function 0x54C read-write 0x00000012 B3 y-intercept of fourth piecewise linear function 0 13 B4 y-intercept of fifth piecewise linear function 0x550 read-write 0x00000124 B4 y-intercept of fifth piecewise linear function 0 13 B5 y-intercept of sixth piecewise linear function 0x554 read-write 0x0000027C B5 y-intercept of sixth piecewise linear function 0 13 T0 End point of first piecewise linear function 0x560 read-write 0x000000E2 T0 End point of first piecewise linear function 0 7 T1 End point of second piecewise linear function 0x564 read-write 0x00000000 T1 End point of second piecewise linear function 0 7 T2 End point of third piecewise linear function 0x568 read-write 0x00000019 T2 End point of third piecewise linear function 0 7 T3 End point of fourth piecewise linear function 0x56C read-write 0x0000003C T3 End point of fourth piecewise linear function 0 7 T4 End point of fifth piecewise linear function 0x570 read-write 0x00000050 T4 End point of fifth piecewise linear function 0 7 RNG Random Number Generator 0x4000D000 0 0x1000 registers RNG 13 RNG 0x20 TASKS_START Task starting the random number generator 0x000 write-only TASKS_START Task starting the random number generator 0 0 Trigger Trigger task 1 TASKS_STOP Task stopping the random number generator 0x004 write-only TASKS_STOP Task stopping the random number generator 0 0 Trigger Trigger task 1 EVENTS_VALRDY Event being generated for every new random number written to the VALUE register 0x100 read-write EVENTS_VALRDY Event being generated for every new random number written to the VALUE register 0 0 NotGenerated Event not generated 0 Generated Event generated 1 SHORTS Shortcuts between local events and tasks 0x200 read-write VALRDY_STOP Shortcut between event VALRDY and task STOP 0 0 Disabled Disable shortcut 0 Enabled Enable shortcut 1 INTENSET Enable interrupt 0x304 read-write VALRDY Write '1' to enable interrupt for event VALRDY 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write VALRDY Write '1' to disable interrupt for event VALRDY 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CONFIG Configuration register 0x504 read-write DERCEN Bias correction 0 0 Disabled Disabled 0 Enabled Enabled 1 VALUE Output random number 0x508 read-only VALUE Generated random number 0 7 ECB AES ECB Mode Encryption 0x4000E000 0 0x1000 registers ECB 14 ECB 0x20 TASKS_STARTECB Start ECB block encrypt 0x000 write-only TASKS_STARTECB Start ECB block encrypt 0 0 Trigger Trigger task 1 TASKS_STOPECB Abort a possible executing ECB operation 0x004 write-only TASKS_STOPECB Abort a possible executing ECB operation 0 0 Trigger Trigger task 1 EVENTS_ENDECB ECB block encrypt complete 0x100 read-write EVENTS_ENDECB ECB block encrypt complete 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_ERRORECB ECB block encrypt aborted because of a STOPECB task or due to an error 0x104 read-write EVENTS_ERRORECB ECB block encrypt aborted because of a STOPECB task or due to an error 0 0 NotGenerated Event not generated 0 Generated Event generated 1 INTENSET Enable interrupt 0x304 read-write ENDECB Write '1' to enable interrupt for event ENDECB 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ERRORECB Write '1' to enable interrupt for event ERRORECB 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write ENDECB Write '1' to disable interrupt for event ENDECB 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ERRORECB Write '1' to disable interrupt for event ERRORECB 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ECBDATAPTR ECB block encrypt memory pointers 0x504 read-write ECBDATAPTR Pointer to the ECB data structure (see Table 1 ECB data structure overview) 0 31 AAR Accelerated Address Resolver 0x4000F000 0 0x1000 registers CCM_AAR 15 AAR 0x20 TASKS_START Start resolving addresses based on IRKs specified in the IRK data structure 0x000 write-only TASKS_START Start resolving addresses based on IRKs specified in the IRK data structure 0 0 Trigger Trigger task 1 TASKS_STOP Stop resolving addresses 0x008 write-only TASKS_STOP Stop resolving addresses 0 0 Trigger Trigger task 1 EVENTS_END Address resolution procedure complete 0x100 read-write EVENTS_END Address resolution procedure complete 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_RESOLVED Address resolved 0x104 read-write EVENTS_RESOLVED Address resolved 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_NOTRESOLVED Address not resolved 0x108 read-write EVENTS_NOTRESOLVED Address not resolved 0 0 NotGenerated Event not generated 0 Generated Event generated 1 INTENSET Enable interrupt 0x304 read-write END Write '1' to enable interrupt for event END 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 RESOLVED Write '1' to enable interrupt for event RESOLVED 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 NOTRESOLVED Write '1' to enable interrupt for event NOTRESOLVED 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write END Write '1' to disable interrupt for event END 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RESOLVED Write '1' to disable interrupt for event RESOLVED 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 NOTRESOLVED Write '1' to disable interrupt for event NOTRESOLVED 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 STATUS Resolution status 0x400 read-only STATUS The IRK that was used last time an address was resolved 0 3 ENABLE Enable AAR 0x500 read-write ENABLE Enable or disable AAR 0 1 Disabled Disable 0 Enabled Enable 3 NIRK Number of IRKs 0x504 read-write 0x00000001 NIRK Number of Identity root keys available in the IRK data structure 0 4 IRKPTR Pointer to IRK data structure 0x508 read-write IRKPTR Pointer to the IRK data structure 0 31 ADDRPTR Pointer to the resolvable address 0x510 read-write ADDRPTR Pointer to the resolvable address (6-bytes) 0 31 SCRATCHPTR Pointer to data area used for temporary storage 0x514 read-write SCRATCHPTR Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved. 0 31 CCM AES CCM Mode Encryption 0x4000F000 AAR 0 0x1000 registers CCM_AAR 15 CCM 0x20 TASKS_KSGEN Start generation of keystream. This operation will stop by itself when completed. 0x000 write-only TASKS_KSGEN Start generation of keystream. This operation will stop by itself when completed. 0 0 Trigger Trigger task 1 TASKS_CRYPT Start encryption/decryption. This operation will stop by itself when completed. 0x004 write-only TASKS_CRYPT Start encryption/decryption. This operation will stop by itself when completed. 0 0 Trigger Trigger task 1 TASKS_STOP Stop encryption/decryption 0x008 write-only TASKS_STOP Stop encryption/decryption 0 0 Trigger Trigger task 1 TASKS_RATEOVERRIDE Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption 0x00C write-only TASKS_RATEOVERRIDE Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption 0 0 Trigger Trigger task 1 EVENTS_ENDKSGEN Keystream generation complete 0x100 read-write EVENTS_ENDKSGEN Keystream generation complete 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_ENDCRYPT Encrypt/decrypt complete 0x104 read-write EVENTS_ENDCRYPT Encrypt/decrypt complete 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_ERROR Deprecated register - CCM error event 0x108 read-write EVENTS_ERROR Deprecated field - CCM error event 0 0 NotGenerated Event not generated 0 Generated Event generated 1 SHORTS Shortcuts between local events and tasks 0x200 read-write ENDKSGEN_CRYPT Shortcut between event ENDKSGEN and task CRYPT 0 0 Disabled Disable shortcut 0 Enabled Enable shortcut 1 INTENSET Enable interrupt 0x304 read-write ENDKSGEN Write '1' to enable interrupt for event ENDKSGEN 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ENDCRYPT Write '1' to enable interrupt for event ENDCRYPT 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ERROR Deprecated intsetfield - Write '1' to enable interrupt for event ERROR 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write ENDKSGEN Write '1' to disable interrupt for event ENDKSGEN 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENDCRYPT Write '1' to disable interrupt for event ENDCRYPT 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ERROR Deprecated intclrfield - Write '1' to disable interrupt for event ERROR 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 MICSTATUS MIC check result 0x400 read-only MICSTATUS The result of the MIC check performed during the previous decryption operation 0 0 CheckFailed MIC check failed 0 CheckPassed MIC check passed 1 ENABLE Enable 0x500 read-write ENABLE Enable or disable CCM 0 1 Disabled Disable 0 Enabled Enable 2 MODE Operation mode 0x504 read-write 0x00000001 MODE The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered. 0 0 Encryption AES CCM packet encryption mode 0 Decryption AES CCM packet decryption mode 1 DATARATE Radio data rate that the CCM shall run synchronous with 16 17 1Mbit 1 Mbps 0 2Mbit 2 Mbps 1 125Kbps 125 Kbps 2 500Kbps 500 Kbps 3 LENGTH Packet length configuration 24 24 Default Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A keystream for packet payloads up to 27 bytes will be generated. 0 Extended Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A keystream for packet payloads up to MAXPACKETSIZE bytes will be generated. 1 CNFPTR Pointer to data structure holding AES key and NONCE vector 0x508 read-write CNFPTR Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) 0 31 INPTR Input pointer 0x50C read-write INPTR Input pointer 0 31 OUTPTR Output pointer 0x510 read-write OUTPTR Output pointer 0 31 SCRATCHPTR Pointer to data area used for temporary storage 0x514 read-write SCRATCHPTR Pointer to a scratch data area used for temporary storage during keystream generation, MIC generation and encryption/decryption. 0 31 MAXPACKETSIZE Length of keystream generated when MODE.LENGTH = Extended. 0x518 read-write 0x000000FB MAXPACKETSIZE Length of keystream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. 0 7 RATEOVERRIDE Data rate override setting. 0x51C read-write 0x00000000 RATEOVERRIDE Data rate override setting. 0 1 1Mbit 1 Mbps 0 2Mbit 2 Mbps 1 125Kbps 125 Kbps 2 500Kbps 500 Kbps 3 WDT Watchdog Timer 0x40010000 0 0x1000 registers WDT 16 WDT 0x20 TASKS_START Start the watchdog 0x000 write-only TASKS_START Start the watchdog 0 0 Trigger Trigger task 1 EVENTS_TIMEOUT Watchdog timeout 0x100 read-write EVENTS_TIMEOUT Watchdog timeout 0 0 NotGenerated Event not generated 0 Generated Event generated 1 INTENSET Enable interrupt 0x304 read-write TIMEOUT Write '1' to enable interrupt for event TIMEOUT 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write TIMEOUT Write '1' to disable interrupt for event TIMEOUT 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RUNSTATUS Run status 0x400 read-only RUNSTATUS Indicates whether or not the watchdog is running 0 0 NotRunning Watchdog not running 0 Running Watchdog is running 1 REQSTATUS Request status 0x404 read-only 0x00000001 RR0 Request status for RR[0] register 0 0 DisabledOrRequested RR[0] register is not enabled, or are already requesting reload 0 EnabledAndUnrequested RR[0] register is enabled, and are not yet requesting reload 1 RR1 Request status for RR[1] register 1 1 DisabledOrRequested RR[1] register is not enabled, or are already requesting reload 0 EnabledAndUnrequested RR[1] register is enabled, and are not yet requesting reload 1 RR2 Request status for RR[2] register 2 2 DisabledOrRequested RR[2] register is not enabled, or are already requesting reload 0 EnabledAndUnrequested RR[2] register is enabled, and are not yet requesting reload 1 RR3 Request status for RR[3] register 3 3 DisabledOrRequested RR[3] register is not enabled, or are already requesting reload 0 EnabledAndUnrequested RR[3] register is enabled, and are not yet requesting reload 1 RR4 Request status for RR[4] register 4 4 DisabledOrRequested RR[4] register is not enabled, or are already requesting reload 0 EnabledAndUnrequested RR[4] register is enabled, and are not yet requesting reload 1 RR5 Request status for RR[5] register 5 5 DisabledOrRequested RR[5] register is not enabled, or are already requesting reload 0 EnabledAndUnrequested RR[5] register is enabled, and are not yet requesting reload 1 RR6 Request status for RR[6] register 6 6 DisabledOrRequested RR[6] register is not enabled, or are already requesting reload 0 EnabledAndUnrequested RR[6] register is enabled, and are not yet requesting reload 1 RR7 Request status for RR[7] register 7 7 DisabledOrRequested RR[7] register is not enabled, or are already requesting reload 0 EnabledAndUnrequested RR[7] register is enabled, and are not yet requesting reload 1 CRV Counter reload value 0x504 read-write 0xFFFFFFFF CRV Counter reload value in number of cycles of the 32.768 kHz clock 0 31 RREN Enable register for reload request registers 0x508 read-write 0x00000001 RR0 Enable or disable RR[0] register 0 0 Disabled Disable RR[0] register 0 Enabled Enable RR[0] register 1 RR1 Enable or disable RR[1] register 1 1 Disabled Disable RR[1] register 0 Enabled Enable RR[1] register 1 RR2 Enable or disable RR[2] register 2 2 Disabled Disable RR[2] register 0 Enabled Enable RR[2] register 1 RR3 Enable or disable RR[3] register 3 3 Disabled Disable RR[3] register 0 Enabled Enable RR[3] register 1 RR4 Enable or disable RR[4] register 4 4 Disabled Disable RR[4] register 0 Enabled Enable RR[4] register 1 RR5 Enable or disable RR[5] register 5 5 Disabled Disable RR[5] register 0 Enabled Enable RR[5] register 1 RR6 Enable or disable RR[6] register 6 6 Disabled Disable RR[6] register 0 Enabled Enable RR[6] register 1 RR7 Enable or disable RR[7] register 7 7 Disabled Disable RR[7] register 0 Enabled Enable RR[7] register 1 CONFIG Configuration register 0x50C read-write 0x00000001 SLEEP Configure the watchdog to either be paused, or kept running, while the CPU is sleeping 0 0 Pause Pause watchdog while the CPU is sleeping 0 Run Keep the watchdog running while the CPU is sleeping 1 HALT Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger 3 3 Pause Pause watchdog while the CPU is halted by the debugger 0 Run Keep the watchdog running while the CPU is halted by the debugger 1 0x8 0x4 RR[%s] Description collection: Reload request n 0x600 write-only RR Reload request register 0 31 Reload Value to request a reload of the watchdog timer 0x6E524635 RTC1 Real time counter 1 0x40011000 RTC1 17 QDEC Quadrature Decoder 0x40012000 0 0x1000 registers QDEC 18 QDEC 0x20 TASKS_START Task starting the quadrature decoder 0x000 write-only TASKS_START Task starting the quadrature decoder 0 0 Trigger Trigger task 1 TASKS_STOP Task stopping the quadrature decoder 0x004 write-only TASKS_STOP Task stopping the quadrature decoder 0 0 Trigger Trigger task 1 TASKS_READCLRACC Read and clear ACC and ACCDBL 0x008 write-only TASKS_READCLRACC Read and clear ACC and ACCDBL 0 0 Trigger Trigger task 1 TASKS_RDCLRACC Read and clear ACC 0x00C write-only TASKS_RDCLRACC Read and clear ACC 0 0 Trigger Trigger task 1 TASKS_RDCLRDBL Read and clear ACCDBL 0x010 write-only TASKS_RDCLRDBL Read and clear ACCDBL 0 0 Trigger Trigger task 1 EVENTS_SAMPLERDY Event being generated for every new sample value written to the SAMPLE register 0x100 read-write EVENTS_SAMPLERDY Event being generated for every new sample value written to the SAMPLE register 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_REPORTRDY Non-null report ready 0x104 read-write EVENTS_REPORTRDY Non-null report ready 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_ACCOF ACC or ACCDBL register overflow 0x108 read-write EVENTS_ACCOF ACC or ACCDBL register overflow 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_DBLRDY Double displacement(s) detected 0x10C read-write EVENTS_DBLRDY Double displacement(s) detected 0 0 NotGenerated Event not generated 0 Generated Event generated 1 EVENTS_STOPPED QDEC has been stopped 0x110 read-write EVENTS_STOPPED QDEC has been stopped 0 0 NotGenerated Event not generated 0 Generated Event generated 1 SHORTS Shortcuts between local events and tasks 0x200 read-write REPORTRDY_READCLRACC Shortcut between event REPORTRDY and task READCLRACC 0 0 Disabled Disable shortcut 0 Enabled Enable shortcut 1 SAMPLERDY_STOP Shortcut between event SAMPLERDY and task STOP 1 1 Disabled Disable shortcut 0 Enabled Enable shortcut 1 REPORTRDY_RDCLRACC Shortcut between event REPORTRDY and task RDCLRACC 2 2 Disabled Disable shortcut 0 Enabled Enable shortcut 1 REPORTRDY_STOP Shortcut between event REPORTRDY and task STOP 3 3 Disabled Disable shortcut 0 Enabled Enable shortcut 1 DBLRDY_RDCLRDBL Shortcut between event DBLRDY and task RDCLRDBL 4 4 Disabled Disable shortcut 0 Enabled Enable shortcut 1 DBLRDY_STOP Shortcut between event DBLRDY and task STOP 5 5 Disabled Disable shortcut 0 Enabled Enable shortcut 1 SAMPLERDY_READCLRACC Shortcut between event SAMPLERDY and task READCLRACC 6 6 Disabled Disable shortcut 0 Enabled Enable shortcut 1 INTENSET Enable interrupt 0x304 read-write SAMPLERDY Write '1' to enable interrupt for event SAMPLERDY 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 REPORTRDY Write '1' to enable interrupt for event REPORTRDY 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ACCOF Write '1' to enable interrupt for event ACCOF 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 DBLRDY Write '1' to enable interrupt for event DBLRDY 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 STOPPED Write '1' to enable interrupt for event STOPPED 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write SAMPLERDY Write '1' to disable interrupt for event SAMPLERDY 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 REPORTRDY Write '1' to disable interrupt for event REPORTRDY 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ACCOF Write '1' to disable interrupt for event ACCOF 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 DBLRDY Write '1' to disable interrupt for event DBLRDY 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 STOPPED Write '1' to disable interrupt for event STOPPED 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENABLE Enable the quadrature decoder 0x500 read-write ENABLE Enable or disable the quadrature decoder 0 0 Disabled Disable 0 Enabled Enable 1 LEDPOL LED output pin polarity 0x504 read-write LEDPOL LED output pin polarity 0 0 ActiveLow Led active on output pin low 0 ActiveHigh Led active on output pin high 1 SAMPLEPER Sample period 0x508 read-write SAMPLEPER Sample period. The SAMPLE register will be updated for every new sample 0 3 128us 128 us 0 256us 256 us 1 512us 512 us 2 1024us 1024 us 3 2048us 2048 us 4 4096us 4096 us 5 8192us 8192 us 6 16384us 16384 us 7 32ms 32768 us 8 65ms 65536 us 9 131ms 131072 us 10 SAMPLE Motion sample value 0x50C read-only int32_t SAMPLE Last motion sample 0 31 REPORTPER Number of samples to be taken before REPORTRDY and DBLRDY events can be generated 0x510 read-write REPORTPER Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated. 0 3 10Smpl 10 samples/report 0 40Smpl 40 samples/report 1 80Smpl 80 samples/report 2 120Smpl 120 samples/report 3 160Smpl 160 samples/report 4 200Smpl 200 samples/report 5 240Smpl 240 samples/report 6 280Smpl 280 samples/report 7 1Smpl 1 sample/report 8 ACC Register accumulating the valid transitions 0x514 read-only int32_t ACC Register accumulating all valid samples (not double transition) read from the SAMPLE register. 0 31 ACCREAD Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task 0x518 read-only int32_t ACCREAD Snapshot of the ACC register. 0 31 PSEL Unspecified QDEC_PSEL read-write 0x51C LED Pin select for LED signal 0x000 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 A Pin select for A signal 0x004 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 B Pin select for B signal 0x008 read-write 0xFFFFFFFF PIN Pin number 0 4 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 DBFEN Enable input debounce filters 0x528 read-write DBFEN Enable input debounce filters 0 0 Disabled Debounce input filters disabled 0 Enabled Debounce input filters enabled 1 LEDPRE Time period the LED is switched ON prior to sampling 0x540 read-write 0x00000010 LEDPRE Period in us the LED is switched on prior to sampling 0 8 ACCDBL Register accumulating the number of detected double transitions 0x544 read-only ACCDBL Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). 0 3 ACCDBLREAD Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task 0x548 read-only ACCDBLREAD Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. 0 3 EGU0 Event generator unit 0 0x40014000 EGU 0 0x1000 registers SWI0_EGU0 20 EGU 0x20 0x10 0x4 TASKS_TRIGGER[%s] Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event 0x000 write-only TASKS_TRIGGER Trigger n for triggering the corresponding TRIGGERED[n] event 0 0 Trigger Trigger task 1 0x10 0x4 EVENTS_TRIGGERED[%s] Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task 0x100 read-write EVENTS_TRIGGERED Event number n generated by triggering the corresponding TRIGGER[n] task 0 0 NotGenerated Event not generated 0 Generated Event generated 1 INTEN Enable or disable interrupt 0x300 read-write TRIGGERED0 Enable or disable interrupt for event TRIGGERED[0] 0 0 Disabled Disable 0 Enabled Enable 1 TRIGGERED1 Enable or disable interrupt for event TRIGGERED[1] 1 1 Disabled Disable 0 Enabled Enable 1 TRIGGERED2 Enable or disable interrupt for event TRIGGERED[2] 2 2 Disabled Disable 0 Enabled Enable 1 TRIGGERED3 Enable or disable interrupt for event TRIGGERED[3] 3 3 Disabled Disable 0 Enabled Enable 1 TRIGGERED4 Enable or disable interrupt for event TRIGGERED[4] 4 4 Disabled Disable 0 Enabled Enable 1 TRIGGERED5 Enable or disable interrupt for event TRIGGERED[5] 5 5 Disabled Disable 0 Enabled Enable 1 TRIGGERED6 Enable or disable interrupt for event TRIGGERED[6] 6 6 Disabled Disable 0 Enabled Enable 1 TRIGGERED7 Enable or disable interrupt for event TRIGGERED[7] 7 7 Disabled Disable 0 Enabled Enable 1 TRIGGERED8 Enable or disable interrupt for event TRIGGERED[8] 8 8 Disabled Disable 0 Enabled Enable 1 TRIGGERED9 Enable or disable interrupt for event TRIGGERED[9] 9 9 Disabled Disable 0 Enabled Enable 1 TRIGGERED10 Enable or disable interrupt for event TRIGGERED[10] 10 10 Disabled Disable 0 Enabled Enable 1 TRIGGERED11 Enable or disable interrupt for event TRIGGERED[11] 11 11 Disabled Disable 0 Enabled Enable 1 TRIGGERED12 Enable or disable interrupt for event TRIGGERED[12] 12 12 Disabled Disable 0 Enabled Enable 1 TRIGGERED13 Enable or disable interrupt for event TRIGGERED[13] 13 13 Disabled Disable 0 Enabled Enable 1 TRIGGERED14 Enable or disable interrupt for event TRIGGERED[14] 14 14 Disabled Disable 0 Enabled Enable 1 TRIGGERED15 Enable or disable interrupt for event TRIGGERED[15] 15 15 Disabled Disable 0 Enabled Enable 1 INTENSET Enable interrupt 0x304 read-write TRIGGERED0 Write '1' to enable interrupt for event TRIGGERED[0] 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED1 Write '1' to enable interrupt for event TRIGGERED[1] 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED2 Write '1' to enable interrupt for event TRIGGERED[2] 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED3 Write '1' to enable interrupt for event TRIGGERED[3] 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED4 Write '1' to enable interrupt for event TRIGGERED[4] 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED5 Write '1' to enable interrupt for event TRIGGERED[5] 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED6 Write '1' to enable interrupt for event TRIGGERED[6] 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED7 Write '1' to enable interrupt for event TRIGGERED[7] 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED8 Write '1' to enable interrupt for event TRIGGERED[8] 8 8 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED9 Write '1' to enable interrupt for event TRIGGERED[9] 9 9 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED10 Write '1' to enable interrupt for event TRIGGERED[10] 10 10 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED11 Write '1' to enable interrupt for event TRIGGERED[11] 11 11 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED12 Write '1' to enable interrupt for event TRIGGERED[12] 12 12 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED13 Write '1' to enable interrupt for event TRIGGERED[13] 13 13 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED14 Write '1' to enable interrupt for event TRIGGERED[14] 14 14 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED15 Write '1' to enable interrupt for event TRIGGERED[15] 15 15 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write TRIGGERED0 Write '1' to disable interrupt for event TRIGGERED[0] 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED1 Write '1' to disable interrupt for event TRIGGERED[1] 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED2 Write '1' to disable interrupt for event TRIGGERED[2] 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED3 Write '1' to disable interrupt for event TRIGGERED[3] 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED4 Write '1' to disable interrupt for event TRIGGERED[4] 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED5 Write '1' to disable interrupt for event TRIGGERED[5] 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED6 Write '1' to disable interrupt for event TRIGGERED[6] 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED7 Write '1' to disable interrupt for event TRIGGERED[7] 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED8 Write '1' to disable interrupt for event TRIGGERED[8] 8 8 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED9 Write '1' to disable interrupt for event TRIGGERED[9] 9 9 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED10 Write '1' to disable interrupt for event TRIGGERED[10] 10 10 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED11 Write '1' to disable interrupt for event TRIGGERED[11] 11 11 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED12 Write '1' to disable interrupt for event TRIGGERED[12] 12 12 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED13 Write '1' to disable interrupt for event TRIGGERED[13] 13 13 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED14 Write '1' to disable interrupt for event TRIGGERED[14] 14 14 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED15 Write '1' to disable interrupt for event TRIGGERED[15] 15 15 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 SWI0 Software interrupt 0 0x40014000 EGU0 SWI 0 0x1000 registers SWI0_EGU0 20 SWI 0x20 UNUSED Unused. 0x000 0x00000000 read-only EGU1 Event generator unit 1 0x40015000 SWI1_EGU1 21 SWI1 Software interrupt 1 0x40015000 EGU1 SWI1_EGU1 21 SWI2 Software interrupt 2 0x40016000 SWI2 22 SWI3 Software interrupt 3 0x40017000 SWI3 23 SWI4 Software interrupt 4 0x40018000 SWI4 24 SWI5 Software interrupt 5 0x40019000 SWI5 25 NVMC Non Volatile Memory Controller 0x4001E000 0 0x1000 registers NVMC 0x20 READY Ready flag 0x400 read-only 0x00000001 READY NVMC is ready or busy 0 0 Busy NVMC is busy (on-going write or erase operation) 0 Ready NVMC is ready 1 CONFIG Configuration register 0x504 read-write WEN Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. 0 1 Ren Read only access 0 Wen Write enabled 1 Een Erase enabled 2 ERASEPAGE Register for erasing a page in code area 0x508 write-only ERASEPAGE Register for starting erase of a page in code area 0 31 ERASEPCR1 Deprecated register - Register for erasing a page in code area, equivalent to ERASEPAGE 0x508 write-only ERASEPAGE ERASEPCR1 Register for erasing a page in code area, equivalent to ERASEPAGE 0 31 ERASEALL Register for erasing all non-volatile user memory 0x50C write-only ERASEALL Erase all non-volatile memory including UICR registers. The erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. 0 0 NoOperation No operation 0 Erase Start chip erase 1 ERASEPCR0 Deprecated register - Register for erasing a page in code area, equivalent to ERASEPAGE 0x510 write-only ERASEPCR0 Register for starting erase of a page in code area, equivalent to ERASEPAGE 0 31 ERASEUICR Register for erasing user information configuration registers 0x514 write-only ERASEUICR Register starting erase of all user information configuration registers. The erase must be enabled using CONFIG.WEN before the UICR can be erased. 0 0 NoOperation No operation 0 Erase Start erase of UICR 1 ERASEPAGEPARTIAL Register for partial erase of a page in code area 0x518 write-only ERASEPAGEPARTIAL Register for starting partial erase of a page in code area 0 31 ERASEPAGEPARTIALCFG Register for partial erase configuration 0x51C read-write 0x0000000A DURATION Duration of the partial erase in milliseconds 0 6 PPI Programmable Peripheral Interconnect 0x4001F000 0 0x1000 registers PPI 0x20 6 0x008 TASKS_CHG[%s] Channel group tasks PPI_TASKS_CHG write-only 0x000 EN Description cluster: Enable channel group n 0x000 write-only EN Enable channel group n 0 0 Trigger Trigger task 1 DIS Description cluster: Disable channel group n 0x004 write-only DIS Disable channel group n 0 0 Trigger Trigger task 1 CHEN Channel enable register 0x500 read-write CH0 Enable or disable channel 0 0 0 Disabled Disable channel 0 Enabled Enable channel 1 CH1 Enable or disable channel 1 1 1 Disabled Disable channel 0 Enabled Enable channel 1 CH2 Enable or disable channel 2 2 2 Disabled Disable channel 0 Enabled Enable channel 1 CH3 Enable or disable channel 3 3 3 Disabled Disable channel 0 Enabled Enable channel 1 CH4 Enable or disable channel 4 4 4 Disabled Disable channel 0 Enabled Enable channel 1 CH5 Enable or disable channel 5 5 5 Disabled Disable channel 0 Enabled Enable channel 1 CH6 Enable or disable channel 6 6 6 Disabled Disable channel 0 Enabled Enable channel 1 CH7 Enable or disable channel 7 7 7 Disabled Disable channel 0 Enabled Enable channel 1 CH8 Enable or disable channel 8 8 8 Disabled Disable channel 0 Enabled Enable channel 1 CH9 Enable or disable channel 9 9 9 Disabled Disable channel 0 Enabled Enable channel 1 CH20 Enable or disable channel 20 20 20 Disabled Disable channel 0 Enabled Enable channel 1 CH21 Enable or disable channel 21 21 21 Disabled Disable channel 0 Enabled Enable channel 1 CH22 Enable or disable channel 22 22 22 Disabled Disable channel 0 Enabled Enable channel 1 CH23 Enable or disable channel 23 23 23 Disabled Disable channel 0 Enabled Enable channel 1 CH24 Enable or disable channel 24 24 24 Disabled Disable channel 0 Enabled Enable channel 1 CH25 Enable or disable channel 25 25 25 Disabled Disable channel 0 Enabled Enable channel 1 CH26 Enable or disable channel 26 26 26 Disabled Disable channel 0 Enabled Enable channel 1 CH27 Enable or disable channel 27 27 27 Disabled Disable channel 0 Enabled Enable channel 1 CH28 Enable or disable channel 28 28 28 Disabled Disable channel 0 Enabled Enable channel 1 CH29 Enable or disable channel 29 29 29 Disabled Disable channel 0 Enabled Enable channel 1 CH30 Enable or disable channel 30 30 30 Disabled Disable channel 0 Enabled Enable channel 1 CH31 Enable or disable channel 31 31 31 Disabled Disable channel 0 Enabled Enable channel 1 CHENSET Channel enable set register 0x504 read-write oneToSet CH0 Channel 0 enable set register. Writing '0' has no effect. 0 0 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH1 Channel 1 enable set register. Writing '0' has no effect. 1 1 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH2 Channel 2 enable set register. Writing '0' has no effect. 2 2 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH3 Channel 3 enable set register. Writing '0' has no effect. 3 3 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH4 Channel 4 enable set register. Writing '0' has no effect. 4 4 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH5 Channel 5 enable set register. Writing '0' has no effect. 5 5 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH6 Channel 6 enable set register. Writing '0' has no effect. 6 6 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH7 Channel 7 enable set register. Writing '0' has no effect. 7 7 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH8 Channel 8 enable set register. Writing '0' has no effect. 8 8 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH9 Channel 9 enable set register. Writing '0' has no effect. 9 9 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH20 Channel 20 enable set register. Writing '0' has no effect. 20 20 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH21 Channel 21 enable set register. Writing '0' has no effect. 21 21 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH22 Channel 22 enable set register. Writing '0' has no effect. 22 22 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH23 Channel 23 enable set register. Writing '0' has no effect. 23 23 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH24 Channel 24 enable set register. Writing '0' has no effect. 24 24 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH25 Channel 25 enable set register. Writing '0' has no effect. 25 25 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH26 Channel 26 enable set register. Writing '0' has no effect. 26 26 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH27 Channel 27 enable set register. Writing '0' has no effect. 27 27 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH28 Channel 28 enable set register. Writing '0' has no effect. 28 28 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH29 Channel 29 enable set register. Writing '0' has no effect. 29 29 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH30 Channel 30 enable set register. Writing '0' has no effect. 30 30 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH31 Channel 31 enable set register. Writing '0' has no effect. 31 31 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CHENCLR Channel enable clear register 0x508 read-write oneToClear CH0 Channel 0 enable clear register. Writing '0' has no effect. 0 0 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH1 Channel 1 enable clear register. Writing '0' has no effect. 1 1 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH2 Channel 2 enable clear register. Writing '0' has no effect. 2 2 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH3 Channel 3 enable clear register. Writing '0' has no effect. 3 3 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH4 Channel 4 enable clear register. Writing '0' has no effect. 4 4 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH5 Channel 5 enable clear register. Writing '0' has no effect. 5 5 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH6 Channel 6 enable clear register. Writing '0' has no effect. 6 6 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH7 Channel 7 enable clear register. Writing '0' has no effect. 7 7 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH8 Channel 8 enable clear register. Writing '0' has no effect. 8 8 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH9 Channel 9 enable clear register. Writing '0' has no effect. 9 9 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH20 Channel 20 enable clear register. Writing '0' has no effect. 20 20 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH21 Channel 21 enable clear register. Writing '0' has no effect. 21 21 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH22 Channel 22 enable clear register. Writing '0' has no effect. 22 22 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH23 Channel 23 enable clear register. Writing '0' has no effect. 23 23 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH24 Channel 24 enable clear register. Writing '0' has no effect. 24 24 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH25 Channel 25 enable clear register. Writing '0' has no effect. 25 25 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH26 Channel 26 enable clear register. Writing '0' has no effect. 26 26 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH27 Channel 27 enable clear register. Writing '0' has no effect. 27 27 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH28 Channel 28 enable clear register. Writing '0' has no effect. 28 28 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH29 Channel 29 enable clear register. Writing '0' has no effect. 29 29 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH30 Channel 30 enable clear register. Writing '0' has no effect. 30 30 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH31 Channel 31 enable clear register. Writing '0' has no effect. 31 31 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 10 0x008 CH[%s] PPI Channel PPI_CH read-write 0x510 EEP Description cluster: Channel n event endpoint 0x000 read-write EEP Pointer to event register. Accepts only addresses to registers from the Event group. 0 31 TEP Description cluster: Channel n task endpoint 0x004 read-write TEP Pointer to task register. Accepts only addresses to registers from the Task group. 0 31 0x6 0x4 CHG[%s] Description collection: Channel group n 0x800 read-write CH0 Include or exclude channel 0 0 0 Excluded Exclude 0 Included Include 1 CH1 Include or exclude channel 1 1 1 Excluded Exclude 0 Included Include 1 CH2 Include or exclude channel 2 2 2 Excluded Exclude 0 Included Include 1 CH3 Include or exclude channel 3 3 3 Excluded Exclude 0 Included Include 1 CH4 Include or exclude channel 4 4 4 Excluded Exclude 0 Included Include 1 CH5 Include or exclude channel 5 5 5 Excluded Exclude 0 Included Include 1 CH6 Include or exclude channel 6 6 6 Excluded Exclude 0 Included Include 1 CH7 Include or exclude channel 7 7 7 Excluded Exclude 0 Included Include 1 CH8 Include or exclude channel 8 8 8 Excluded Exclude 0 Included Include 1 CH9 Include or exclude channel 9 9 9 Excluded Exclude 0 Included Include 1 CH20 Include or exclude channel 20 20 20 Excluded Exclude 0 Included Include 1 CH21 Include or exclude channel 21 21 21 Excluded Exclude 0 Included Include 1 CH22 Include or exclude channel 22 22 22 Excluded Exclude 0 Included Include 1 CH23 Include or exclude channel 23 23 23 Excluded Exclude 0 Included Include 1 CH24 Include or exclude channel 24 24 24 Excluded Exclude 0 Included Include 1 CH25 Include or exclude channel 25 25 25 Excluded Exclude 0 Included Include 1 CH26 Include or exclude channel 26 26 26 Excluded Exclude 0 Included Include 1 CH27 Include or exclude channel 27 27 27 Excluded Exclude 0 Included Include 1 CH28 Include or exclude channel 28 28 28 Excluded Exclude 0 Included Include 1 CH29 Include or exclude channel 29 29 29 Excluded Exclude 0 Included Include 1 CH30 Include or exclude channel 30 30 30 Excluded Exclude 0 Included Include 1 CH31 Include or exclude channel 31 31 31 Excluded Exclude 0 Included Include 1 32 0x004 FORK[%s] Fork PPI_FORK read-write 0x910 TEP Description cluster: Channel n task endpoint 0x000 read-write TEP Pointer to task register 0 31